Hierarchical architecture for network-on-chip platform

Liang Yu Lin*, Huang Kai Lin, Cheng Yeh Wang, Lan-Da Van, Jing Yang Jou

*此作品的通信作者

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

In this paper. we propose one hierarchical 2-D mesh Network-on-chip (NoC) platform to support applications with the complexity of several hundreds of tasks or with huge amount of transmission data. Moreover, applying the task binding method by considering communication amount. communication data contention and bandwidlh penalty to enhance the system overall performance of the new architecture. Modeling the NoC system data transmission behavior at system level is applied to predict system overall performance and an automatic NoC system performance simulation tool is also built. Therefore, architecture and designers can predict the system performance and obtain all parameters of the designed platform at system abstraction level. The experimental results show that the overall system throughput. the latency, and the saving of redundant transactions are improved by 27%, 14.4% and 21.8% respectively under the communication dominated situation.

原文English
主出版物標題2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
頁面343-346
頁數4
DOIs
出版狀態Published - 1 十二月 2009
事件2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
持續時間: 28 四月 200930 四月 2009

出版系列

名字2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Conference

Conference2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
國家/地區Taiwan
城市Hsinchu
期間28/04/0930/04/09

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