TY - GEN
T1 - Hierarchical architecture for network-on-chip platform
AU - Lin, Liang Yu
AU - Lin, Huang Kai
AU - Wang, Cheng Yeh
AU - Van, Lan-Da
AU - Jou, Jing Yang
PY - 2009/12/1
Y1 - 2009/12/1
N2 - In this paper. we propose one hierarchical 2-D mesh Network-on-chip (NoC) platform to support applications with the complexity of several hundreds of tasks or with huge amount of transmission data. Moreover, applying the task binding method by considering communication amount. communication data contention and bandwidlh penalty to enhance the system overall performance of the new architecture. Modeling the NoC system data transmission behavior at system level is applied to predict system overall performance and an automatic NoC system performance simulation tool is also built. Therefore, architecture and designers can predict the system performance and obtain all parameters of the designed platform at system abstraction level. The experimental results show that the overall system throughput. the latency, and the saving of redundant transactions are improved by 27%, 14.4% and 21.8% respectively under the communication dominated situation.
AB - In this paper. we propose one hierarchical 2-D mesh Network-on-chip (NoC) platform to support applications with the complexity of several hundreds of tasks or with huge amount of transmission data. Moreover, applying the task binding method by considering communication amount. communication data contention and bandwidlh penalty to enhance the system overall performance of the new architecture. Modeling the NoC system data transmission behavior at system level is applied to predict system overall performance and an automatic NoC system performance simulation tool is also built. Therefore, architecture and designers can predict the system performance and obtain all parameters of the designed platform at system abstraction level. The experimental results show that the overall system throughput. the latency, and the saving of redundant transactions are improved by 27%, 14.4% and 21.8% respectively under the communication dominated situation.
UR - http://www.scopus.com/inward/record.url?scp=77950643838&partnerID=8YFLogxK
U2 - 10.1109/VDAT.2009.5158165
DO - 10.1109/VDAT.2009.5158165
M3 - Conference contribution
AN - SCOPUS:77950643838
SN - 9781424427826
T3 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
SP - 343
EP - 346
BT - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
T2 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Y2 - 28 April 2009 through 30 April 2009
ER -