摘要
For a reconfigurable architecture, the harvest rate is the expected percentage of defect-free processors that can be connected into the desired topology. In this paper, we give an analytical estimation for the harvest rate of reconfigurable multipipelines based on the following model: There are n pipelines each with m stages, where each stage of a pipeline is defective with identical independent probability 0.5 and spare wires are provided for reconfiguration. By formulating the "shifting" reconfiguration as weighted chains in a partial ordered set, we prove when n = Θ(m), the harvest rate is between 34% and 72%.
原文 | English |
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頁(從 - 到) | 1200-1203 |
頁數 | 4 |
期刊 | IEEE Transactions on Computers |
卷 | 45 |
發行號 | 10 |
DOIs | |
出版狀態 | Published - 1996 |