TY - GEN
T1 - Hardwiring the OS kernel into a Java application processor
AU - Tsai, Chun-Jen
AU - Lin, Cheng Ju
AU - Chen, Cheng Yang
AU - Lin, Yan Hung
AU - Ji, Wei Jhong
AU - Hong, Sheng Di
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/7/28
Y1 - 2017/7/28
N2 - This paper presents the design and implementation of a hardwired OS kernel circuitry inside a Java application processor to provide the system services that are traditionally implemented in software. The hardwired system functions in the proposed SoC include the thread manager, the memory manager, and the I/O subsystem interface. There are many advantages in making the OS kernel a hardware component, such as a fast system boot time, highly efficient single-core multi-Thread context-switching performance, and a better potential for supporting a complex multi-level memory subsystem. In addition, since the target application processor used in this paper is based on a Java processor, the system is not susceptible to the stack and pointer-based security attacks that are common to the register-based processors. Full-system performance evaluations on an FPGA show that the proposed system is very promising for deeply-embedded multi-Thread applications.
AB - This paper presents the design and implementation of a hardwired OS kernel circuitry inside a Java application processor to provide the system services that are traditionally implemented in software. The hardwired system functions in the proposed SoC include the thread manager, the memory manager, and the I/O subsystem interface. There are many advantages in making the OS kernel a hardware component, such as a fast system boot time, highly efficient single-core multi-Thread context-switching performance, and a better potential for supporting a complex multi-level memory subsystem. In addition, since the target application processor used in this paper is based on a Java processor, the system is not susceptible to the stack and pointer-based security attacks that are common to the register-based processors. Full-system performance evaluations on an FPGA show that the proposed system is very promising for deeply-embedded multi-Thread applications.
KW - Embedded application processors
KW - Hardware memory managers
KW - Hardware thread mangers
KW - Java processors
UR - http://www.scopus.com/inward/record.url?scp=85028063968&partnerID=8YFLogxK
U2 - 10.1109/ASAP.2017.7995259
DO - 10.1109/ASAP.2017.7995259
M3 - Conference contribution
AN - SCOPUS:85028063968
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 53
EP - 60
BT - 2017 IEEE 28th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 28th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2017
Y2 - 10 July 2017 through 12 July 2017
ER -