Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation

Lan-Da Van; Tsung Che Lu; Tzyy Ping Jung; Jo Fu Wang

doi:10.1109/ICASSP.2019.8682997

Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation

Lan-Da Van, Tsung Che Lu, Tzyy Ping Jung, Jo Fu Wang

資訊科學與工程研究所

研究成果: Conference contribution › 同行評審

10 引文斯高帕斯（Scopus）

摘要

This paper presents a hardware-oriented memory-limited online FastICA algorithm and its hardware architecture and implementation for eight-channel electroencephalogram (EEG) signal separation. The online algorithm integrates the data overlapping, garbage detection, channel permutation, and momentum-controlled weight update schemes to stabilize the order of the decomposed source signals across time. This study also realizes the algorithm into a hardware architecture and implementation with a core area of 1.469x1.469 mm² in a TSMC 90 nm process. The resulting power dissipation for eight-channel EEG signal separation is 65 mW@100 MHz at 1V.

原文	English
主出版物標題	2019 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 - Proceedings
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	1438-1442
頁數	5
ISBN（電子）	9781479981311
DOIs	https://doi.org/10.1109/ICASSP.2019.8682997
出版狀態	Published - 5月 2019
事件	44th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 - Brighton, 英國持續時間: 12 5月 2019 → 17 5月 2019

出版系列

名字	ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
卷	2019-May
ISSN（列印）	1520-6149

Conference

Conference	44th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019
國家/地區	英國
城市	Brighton
期間	12/05/19 → 17/05/19

存取文件

10.1109/ICASSP.2019.8682997

其它文件與鏈接

Link to publication in Scopus

引用此

Van, L.-D., Lu, T. C., Jung, T. P., & Wang, J. F. (2019). Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation. 於 2019 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 - Proceedings (頁 1438-1442). 文章 8682997 (ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings; 卷 2019-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICASSP.2019.8682997

Van, Lan-Da ; Lu, Tsung Che ; Jung, Tzyy Ping 等. / Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation. 2019 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 頁 1438-1442 (ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings).

@inproceedings{b362798fb2dd43c88dc4d035065ee73b,

title = "Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation",

abstract = "This paper presents a hardware-oriented memory-limited online FastICA algorithm and its hardware architecture and implementation for eight-channel electroencephalogram (EEG) signal separation. The online algorithm integrates the data overlapping, garbage detection, channel permutation, and momentum-controlled weight update schemes to stabilize the order of the decomposed source signals across time. This study also realizes the algorithm into a hardware architecture and implementation with a core area of 1.469x1.469 mm2 in a TSMC 90 nm process. The resulting power dissipation for eight-channel EEG signal separation is 65 mW@100 MHz at 1V.",

keywords = "Blind signal separation, EEG, and hardware implementation, component/channel switch, fast independent component analysis (FastICA)",

author = "Lan-Da Van and Lu, {Tsung Che} and Jung, {Tzyy Ping} and Wang, {Jo Fu}",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 44th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 ; Conference date: 12-05-2019 Through 17-05-2019",

year = "2019",

month = may,

doi = "10.1109/ICASSP.2019.8682997",

language = "English",

series = "ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1438--1442",

booktitle = "2019 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 - Proceedings",

address = "美國",

}

Van, L-D, Lu, TC, Jung, TP & Wang, JF 2019, Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation. 於 2019 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 - Proceedings., 8682997, ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, 卷 2019-May, Institute of Electrical and Electronics Engineers Inc., 頁 1438-1442, 44th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019, Brighton, 英國, 12/05/19. https://doi.org/10.1109/ICASSP.2019.8682997

Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation. / Van, Lan-Da; Lu, Tsung Che; Jung, Tzyy Ping 等.
2019 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. p. 1438-1442 8682997 (ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings; 卷 2019-May).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation

AU - Van, Lan-Da

AU - Lu, Tsung Che

AU - Jung, Tzyy Ping

AU - Wang, Jo Fu

PY - 2019/5

Y1 - 2019/5

N2 - This paper presents a hardware-oriented memory-limited online FastICA algorithm and its hardware architecture and implementation for eight-channel electroencephalogram (EEG) signal separation. The online algorithm integrates the data overlapping, garbage detection, channel permutation, and momentum-controlled weight update schemes to stabilize the order of the decomposed source signals across time. This study also realizes the algorithm into a hardware architecture and implementation with a core area of 1.469x1.469 mm2 in a TSMC 90 nm process. The resulting power dissipation for eight-channel EEG signal separation is 65 mW@100 MHz at 1V.

AB - This paper presents a hardware-oriented memory-limited online FastICA algorithm and its hardware architecture and implementation for eight-channel electroencephalogram (EEG) signal separation. The online algorithm integrates the data overlapping, garbage detection, channel permutation, and momentum-controlled weight update schemes to stabilize the order of the decomposed source signals across time. This study also realizes the algorithm into a hardware architecture and implementation with a core area of 1.469x1.469 mm2 in a TSMC 90 nm process. The resulting power dissipation for eight-channel EEG signal separation is 65 mW@100 MHz at 1V.

KW - Blind signal separation

KW - EEG

KW - and hardware implementation

KW - component/channel switch

KW - fast independent component analysis (FastICA)

UR - http://www.scopus.com/inward/record.url?scp=85068981811&partnerID=8YFLogxK

U2 - 10.1109/ICASSP.2019.8682997

DO - 10.1109/ICASSP.2019.8682997

M3 - Conference contribution

AN - SCOPUS:85068981811

T3 - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

SP - 1438

EP - 1442

BT - 2019 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 44th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019

Y2 - 12 May 2019 through 17 May 2019

ER -

Van LD, Lu TC, Jung TP, Wang JF. Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation. 於 2019 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2019. p. 1438-1442. 8682997. (ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings). doi: 10.1109/ICASSP.2019.8682997

Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation

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