Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation

Lan-Da Van, Tsung Che Lu, Tzyy Ping Jung, Jo Fu Wang

研究成果: Conference contribution同行評審

10 引文 斯高帕斯(Scopus)

摘要

This paper presents a hardware-oriented memory-limited online FastICA algorithm and its hardware architecture and implementation for eight-channel electroencephalogram (EEG) signal separation. The online algorithm integrates the data overlapping, garbage detection, channel permutation, and momentum-controlled weight update schemes to stabilize the order of the decomposed source signals across time. This study also realizes the algorithm into a hardware architecture and implementation with a core area of 1.469x1.469 mm2 in a TSMC 90 nm process. The resulting power dissipation for eight-channel EEG signal separation is 65 mW@100 MHz at 1V.

原文English
主出版物標題2019 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1438-1442
頁數5
ISBN(電子)9781479981311
DOIs
出版狀態Published - 5月 2019
事件44th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 - Brighton, 英國
持續時間: 12 5月 201917 5月 2019

出版系列

名字ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
2019-May
ISSN(列印)1520-6149

Conference

Conference44th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019
國家/地區英國
城市Brighton
期間12/05/1917/05/19

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