Hardware nested looping of parameterized and embedded DSP core

Ya Lan Tsao; Wei Hao Chen; Wen Sheng Cheng; Maw Ching Lin; Shyh-Jye Jou

doi:10.1109/SOC.2003.1241460

Hardware nested looping of parameterized and embedded DSP core

Ya Lan Tsao, Wei Hao Chen, Wen Sheng Cheng, Maw Ching Lin, Shyh-Jye Jou

電子研究所

研究成果: Conference contribution › 同行評審

5 引文斯高帕斯（Scopus）

摘要

In this paper, a hardware nested looping structure is proposed for a parameterized and embedded DSP core. The zero-overhead looping scheme used does not cause any clock latency during loop execution. An optional buffer memory for the instructions in the loop is used to save power consumption of the memory access during the transaction of the program memory fetch. The size of instruction buffer and nested loop depth are parameterized parameters in our NCU-DSP core design. Design examples show that there is only a 3% hardware overhead for the nested hardware looping.

原文	English
主出版物標題	Proceedings - IEEE International SOC Conference, SOCC 2003
編輯	Dong S. Ha, Richard Auletta, John Chickanosky
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	49-52
頁數	4
ISBN（電子）	0780381823, 9780780381827
DOIs	https://doi.org/10.1109/SOC.2003.1241460
出版狀態	Published - 1 1月 2003
事件	IEEE International SOC Conference, SOCC 2003 - Portland, 美國持續時間: 17 9月 2003 → 20 9月 2003

出版系列

名字	Proceedings - IEEE International SOC Conference, SOCC 2003

Conference

Conference	IEEE International SOC Conference, SOCC 2003
國家/地區	美國
城市	Portland
期間	17/09/03 → 20/09/03

UN SDG

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10.1109/SOC.2003.1241460

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Link to publication in Scopus

引用此

Tsao, Y. L., Chen, W. H., Cheng, W. S., Lin, M. C., & Jou, S.-J. (2003). Hardware nested looping of parameterized and embedded DSP core. 於 D. S. Ha, R. Auletta, & J. Chickanosky (編輯), Proceedings - IEEE International SOC Conference, SOCC 2003 (頁 49-52). 文章 1241460 (Proceedings - IEEE International SOC Conference, SOCC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SOC.2003.1241460

Tsao, Ya Lan ; Chen, Wei Hao ; Cheng, Wen Sheng 等. / Hardware nested looping of parameterized and embedded DSP core. Proceedings - IEEE International SOC Conference, SOCC 2003. 編輯 / Dong S. Ha ; Richard Auletta ; John Chickanosky. Institute of Electrical and Electronics Engineers Inc., 2003. 頁 49-52 (Proceedings - IEEE International SOC Conference, SOCC 2003).

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title = "Hardware nested looping of parameterized and embedded DSP core",

abstract = "In this paper, a hardware nested looping structure is proposed for a parameterized and embedded DSP core. The zero-overhead looping scheme used does not cause any clock latency during loop execution. An optional buffer memory for the instructions in the loop is used to save power consumption of the memory access during the transaction of the program memory fetch. The size of instruction buffer and nested loop depth are parameterized parameters in our NCU-DSP core design. Design examples show that there is only a 3% hardware overhead for the nested hardware looping.",

keywords = "Application specific integrated circuits, Cities and towns, Communication system control, Digital signal processing, Digital signal processing chips, Energy consumption, Hardware, Hazards, Pipelines, Signal processing algorithms",

author = "Tsao, {Ya Lan} and Chen, {Wei Hao} and Cheng, {Wen Sheng} and Lin, {Maw Ching} and Shyh-Jye Jou",

year = "2003",

month = jan,

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doi = "10.1109/SOC.2003.1241460",

language = "English",

series = "Proceedings - IEEE International SOC Conference, SOCC 2003",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "49--52",

editor = "Ha, {Dong S.} and Richard Auletta and John Chickanosky",

booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2003",

address = "美國",

note = "IEEE International SOC Conference, SOCC 2003 ; Conference date: 17-09-2003 Through 20-09-2003",

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Tsao, YL, Chen, WH, Cheng, WS, Lin, MC & Jou, S-J 2003, Hardware nested looping of parameterized and embedded DSP core. 於 DS Ha, R Auletta & J Chickanosky (編輯), Proceedings - IEEE International SOC Conference, SOCC 2003., 1241460, Proceedings - IEEE International SOC Conference, SOCC 2003, Institute of Electrical and Electronics Engineers Inc., 頁 49-52, IEEE International SOC Conference, SOCC 2003, Portland, 美國, 17/09/03. https://doi.org/10.1109/SOC.2003.1241460

Hardware nested looping of parameterized and embedded DSP core. / Tsao, Ya Lan; Chen, Wei Hao; Cheng, Wen Sheng 等.
Proceedings - IEEE International SOC Conference, SOCC 2003. 編輯 / Dong S. Ha; Richard Auletta; John Chickanosky. Institute of Electrical and Electronics Engineers Inc., 2003. p. 49-52 1241460 (Proceedings - IEEE International SOC Conference, SOCC 2003).

研究成果: Conference contribution › 同行評審

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T1 - Hardware nested looping of parameterized and embedded DSP core

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AU - Chen, Wei Hao

AU - Cheng, Wen Sheng

AU - Lin, Maw Ching

AU - Jou, Shyh-Jye

PY - 2003/1/1

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N2 - In this paper, a hardware nested looping structure is proposed for a parameterized and embedded DSP core. The zero-overhead looping scheme used does not cause any clock latency during loop execution. An optional buffer memory for the instructions in the loop is used to save power consumption of the memory access during the transaction of the program memory fetch. The size of instruction buffer and nested loop depth are parameterized parameters in our NCU-DSP core design. Design examples show that there is only a 3% hardware overhead for the nested hardware looping.

AB - In this paper, a hardware nested looping structure is proposed for a parameterized and embedded DSP core. The zero-overhead looping scheme used does not cause any clock latency during loop execution. An optional buffer memory for the instructions in the loop is used to save power consumption of the memory access during the transaction of the program memory fetch. The size of instruction buffer and nested loop depth are parameterized parameters in our NCU-DSP core design. Design examples show that there is only a 3% hardware overhead for the nested hardware looping.

KW - Application specific integrated circuits

KW - Cities and towns

KW - Communication system control

KW - Digital signal processing

KW - Digital signal processing chips

KW - Energy consumption

KW - Hardware

KW - Hazards

KW - Pipelines

KW - Signal processing algorithms

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U2 - 10.1109/SOC.2003.1241460

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M3 - Conference contribution

AN - SCOPUS:79951738127

T3 - Proceedings - IEEE International SOC Conference, SOCC 2003

SP - 49

EP - 52

BT - Proceedings - IEEE International SOC Conference, SOCC 2003

A2 - Ha, Dong S.

A2 - Auletta, Richard

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PB - Institute of Electrical and Electronics Engineers Inc.

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Tsao YL, Chen WH, Cheng WS, Lin MC, Jou SJ. Hardware nested looping of parameterized and embedded DSP core. 於 Ha DS, Auletta R, Chickanosky J, 編輯, Proceedings - IEEE International SOC Conference, SOCC 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 49-52. 1241460. (Proceedings - IEEE International SOC Conference, SOCC 2003). doi: 10.1109/SOC.2003.1241460

Hardware nested looping of parameterized and embedded DSP core

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