Hardware nested looping of parameterized and embedded DSP core

Ya Lan Tsao, Wei Hao Chen, Wen Sheng Cheng, Maw Ching Lin, Shyh-Jye Jou

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

In this paper, a hardware nested looping structure is proposed for a parameterized and embedded DSP core. The zero-overhead looping scheme used does not cause any clock latency during loop execution. An optional buffer memory for the instructions in the loop is used to save power consumption of the memory access during the transaction of the program memory fetch. The size of instruction buffer and nested loop depth are parameterized parameters in our NCU-DSP core design. Design examples show that there is only a 3% hardware overhead for the nested hardware looping.

原文English
主出版物標題Proceedings - IEEE International SOC Conference, SOCC 2003
編輯Dong S. Ha, Richard Auletta, John Chickanosky
發行者Institute of Electrical and Electronics Engineers Inc.
頁面49-52
頁數4
ISBN(電子)0780381823, 9780780381827
DOIs
出版狀態Published - 1 1月 2003
事件IEEE International SOC Conference, SOCC 2003 - Portland, United States
持續時間: 17 9月 200320 9月 2003

出版系列

名字Proceedings - IEEE International SOC Conference, SOCC 2003

Conference

ConferenceIEEE International SOC Conference, SOCC 2003
國家/地區United States
城市Portland
期間17/09/0320/09/03

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