Hardware nested loop with buffer of parameterized and embedded DSP core

A hardware nested looping structure with an instruction buffer memory is proposed in this paper for a parameterized and embedded DSP core. An optional buffer memory for the loop instructions is used to save much of the memory access power consumption during the program memory fetching transaction. The size of the instruction buffer memory and the maximum nested loop depth are parameterized parameters. A design example shows that the hardware overhead for the nested hardware looping scheme is only 4% and saves 13% power consumption.