Hardware-efficient implementations for discrete function transforms using LUT-based FPGAs

Keyphrases

• Algorithmic Level 33%
• Bit Level 66%
• Buffer Design 33%
• Device Characteristics 33%
• Discrete Function 100%
• Distributed Arithmetic 100%
• Efficient Implementation 100%
• FPGA Device 66%
• Grain Size 33%
• Hardware Cost 66%
• Hardware Efficiency 100%
• Input Buffer 33%
• Multiplierless 33%
• Proposed Design 33%

Engineering

• Adders 25%
• Algorithm Level 25%
• Efficient Implementation 100%
• Field Programmable Gate Arrays 100%
• Free Design 25%
• Grain Level 25%
• Hardware Cost 50%
• Input Buffer 25%