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Hardware-efficient DFT designs with cyclic convolution and subexpression sharing
Tian-Sheuan Chang
,
Jiun-In Guo
, Chein Wei Jen
電子研究所
研究成果
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Article
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引文 斯高帕斯（Scopus）
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Keyphrases
Hardware Efficiency
100%
Discrete Fourier Transform
100%
Cyclic Convolution
100%
Proposed Design
20%
Powers of Two
20%
Hardware Sharing
20%
Word-level
20%
Memory-based
20%
Constant Property
20%
Numerical Properties
20%
Bit Level
20%
Complex Constants
20%
Shift Operation
20%
Transform Coefficient
20%
Discrete Fourier Transform Coefficients
20%
Common Subexpression Sharing
20%
Constant multiplication
20%
Computer Science
Fourier Transform
100%
Cyclic Convolution
100%
Computer Hardware
100%
Input/Output
33%
Presented Approach
33%
Transform Coefficient
16%
Shift Operation
16%
Hardware Level
16%
Discrete Cosine Transform
16%
Engineering
Cyclic Convolution
100%
Fourier Transform Design
100%
Discrete Fourier Transform
100%
Output Sample
16%
Shift Operation
16%
Mathematics
Discrete Fourier Transform
100%
Convolution
100%
Convolution Form
16%
Discrete Cosine Transform
16%