Hardware architecture design of hybrid distributed video coding with frame level coding mode selection

Chieh Chuan Chiu; Hsin Fang Wu; Shao Yi Chien; Chia-Han Lee; V. Srinivasa Somayazulu; Yen Kuang Chen

Hardware architecture design of hybrid distributed video coding with frame level coding mode selection

Chieh Chuan Chiu^*, Hsin Fang Wu, Shao Yi Chien, Chia-Han Lee, V. Srinivasa Somayazulu, Yen Kuang Chen

^*此作品的通信作者

電機工程學系

研究成果: Conference contribution › 同行評審

2 引文斯高帕斯（Scopus）

摘要

Distributed video coding (DVC), a new video coding paradigm based on Slepian-Wolf and Wyner-Ziv theories, is a promising solution for implementing low-power and low-cost distributed wireless video sensors since most of the computation load is moved from the encoder to the decoder. In this paper, the hardware architecture design of an efficient distributed video coding system, hybrid DVC with frame-level coding mode selection, is proposed. With the fully block-pipelined architecture, coding mode pre-decision, and specially-designed LDPC code engine, the proposed hardware is an efficient solution for distributed video sensors with high rate-distortion performance.

原文	English
主出版物標題	2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012
出版狀態	Published - 2012
事件	2012 4th Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012 - Hollywood, CA, 美國持續時間: 3 12月 2012 → 6 12月 2012

出版系列

名字	2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012

Conference

Conference	2012 4th Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012
國家/地區	美國
城市	Hollywood, CA
期間	3/12/12 → 6/12/12

其它文件與鏈接

Link to publication in Scopus

引用此

Chiu, C. C., Wu, H. F., Chien, S. Y., Lee, C.-H., Somayazulu, V. S., & Chen, Y. K. (2012). Hardware architecture design of hybrid distributed video coding with frame level coding mode selection. 於 2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012 文章 6411963 (2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012).

Chiu, Chieh Chuan ; Wu, Hsin Fang ; Chien, Shao Yi 等. / Hardware architecture design of hybrid distributed video coding with frame level coding mode selection. 2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012. 2012. (2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012).

@inproceedings{8c396ee6d0bf43b2923e7a43c9531751,

title = "Hardware architecture design of hybrid distributed video coding with frame level coding mode selection",

abstract = "Distributed video coding (DVC), a new video coding paradigm based on Slepian-Wolf and Wyner-Ziv theories, is a promising solution for implementing low-power and low-cost distributed wireless video sensors since most of the computation load is moved from the encoder to the decoder. In this paper, the hardware architecture design of an efficient distributed video coding system, hybrid DVC with frame-level coding mode selection, is proposed. With the fully block-pipelined architecture, coding mode pre-decision, and specially-designed LDPC code engine, the proposed hardware is an efficient solution for distributed video sensors with high rate-distortion performance.",

author = "Chiu, {Chieh Chuan} and Wu, {Hsin Fang} and Chien, {Shao Yi} and Chia-Han Lee and Somayazulu, {V. Srinivasa} and Chen, {Yen Kuang}",

year = "2012",

language = "English",

isbn = "9780615700502",

series = "2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012",

booktitle = "2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012",

note = "2012 4th Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012 ; Conference date: 03-12-2012 Through 06-12-2012",

}

Chiu, CC, Wu, HF, Chien, SY, Lee, C-H, Somayazulu, VS & Chen, YK 2012, Hardware architecture design of hybrid distributed video coding with frame level coding mode selection. 於 2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012., 6411963, 2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012, 2012 4th Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012, Hollywood, CA, 美國, 3/12/12.

Hardware architecture design of hybrid distributed video coding with frame level coding mode selection. / Chiu, Chieh Chuan; Wu, Hsin Fang; Chien, Shao Yi 等.
2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012. 2012. 6411963 (2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Hardware architecture design of hybrid distributed video coding with frame level coding mode selection

AU - Chiu, Chieh Chuan

AU - Wu, Hsin Fang

AU - Chien, Shao Yi

AU - Lee, Chia-Han

AU - Somayazulu, V. Srinivasa

AU - Chen, Yen Kuang

PY - 2012

Y1 - 2012

N2 - Distributed video coding (DVC), a new video coding paradigm based on Slepian-Wolf and Wyner-Ziv theories, is a promising solution for implementing low-power and low-cost distributed wireless video sensors since most of the computation load is moved from the encoder to the decoder. In this paper, the hardware architecture design of an efficient distributed video coding system, hybrid DVC with frame-level coding mode selection, is proposed. With the fully block-pipelined architecture, coding mode pre-decision, and specially-designed LDPC code engine, the proposed hardware is an efficient solution for distributed video sensors with high rate-distortion performance.

AB - Distributed video coding (DVC), a new video coding paradigm based on Slepian-Wolf and Wyner-Ziv theories, is a promising solution for implementing low-power and low-cost distributed wireless video sensors since most of the computation load is moved from the encoder to the decoder. In this paper, the hardware architecture design of an efficient distributed video coding system, hybrid DVC with frame-level coding mode selection, is proposed. With the fully block-pipelined architecture, coding mode pre-decision, and specially-designed LDPC code engine, the proposed hardware is an efficient solution for distributed video sensors with high rate-distortion performance.

UR - http://www.scopus.com/inward/record.url?scp=84874448037&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84874448037

SN - 9780615700502

T3 - 2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012

BT - 2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012

T2 - 2012 4th Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012

Y2 - 3 December 2012 through 6 December 2012

ER -

Chiu CC, Wu HF, Chien SY, Lee CH, Somayazulu VS, Chen YK. Hardware architecture design of hybrid distributed video coding with frame level coding mode selection. 於 2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012. 2012. 6411963. (2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012).

Hardware architecture design of hybrid distributed video coding with frame level coding mode selection

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出版系列

Conference

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