Halo and LDD engineering for multiple vTH high performance analog CMOS devices

Jyh-Chyurn Guo

doi:10.1109/TSM.2007.901408

Halo and LDD engineering for multiple vTH high performance analog CMOS devices

Jyh-Chyurn Guo^*

^*此作品的通信作者

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

摘要

High performance analog (HPA) CMOS devices with multiple threshold voltages have been successfully fabricated in a 0.13-μm logic-based mixed-signal CMOS process on a single chip. The HPA devices demonstrate superior drivability, dc gain, matching, and reliability using an optimized halo and lightly doped drain (LLD) engineering approach combined with a unique dual gate oxide module for aggressive gate oxide thickness scaling.

原文	English
頁（從 - 到）	313-321
頁數	9
期刊	IEEE Transactions on Semiconductor Manufacturing
卷	20
發行號	3
DOIs	https://doi.org/10.1109/TSM.2007.901408
出版狀態	Published - 1 8月 2007

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10.1109/TSM.2007.901408

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@article{4634ac99cd884e49bcc665893ddd10cc,

title = "Halo and LDD engineering for multiple vTH high performance analog CMOS devices",

abstract = "High performance analog (HPA) CMOS devices with multiple threshold voltages have been successfully fabricated in a 0.13-μm logic-based mixed-signal CMOS process on a single chip. The HPA devices demonstrate superior drivability, dc gain, matching, and reliability using an optimized halo and lightly doped drain (LLD) engineering approach combined with a unique dual gate oxide module for aggressive gate oxide thickness scaling.",

keywords = "Dual gate oxide, Halo, High performance analog (HPA), LDD engineering, Multiple threshold voltages",

author = "Jyh-Chyurn Guo",

year = "2007",

month = aug,

day = "1",

doi = "10.1109/TSM.2007.901408",

language = "English",

volume = "20",

pages = "313--321",

journal = "IEEE Transactions on Semiconductor Manufacturing",

issn = "0894-6507",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - Halo and LDD engineering for multiple vTH high performance analog CMOS devices

AU - Guo, Jyh-Chyurn

PY - 2007/8/1

Y1 - 2007/8/1

N2 - High performance analog (HPA) CMOS devices with multiple threshold voltages have been successfully fabricated in a 0.13-μm logic-based mixed-signal CMOS process on a single chip. The HPA devices demonstrate superior drivability, dc gain, matching, and reliability using an optimized halo and lightly doped drain (LLD) engineering approach combined with a unique dual gate oxide module for aggressive gate oxide thickness scaling.

AB - High performance analog (HPA) CMOS devices with multiple threshold voltages have been successfully fabricated in a 0.13-μm logic-based mixed-signal CMOS process on a single chip. The HPA devices demonstrate superior drivability, dc gain, matching, and reliability using an optimized halo and lightly doped drain (LLD) engineering approach combined with a unique dual gate oxide module for aggressive gate oxide thickness scaling.

KW - Dual gate oxide

KW - Halo

KW - High performance analog (HPA)

KW - LDD engineering

KW - Multiple threshold voltages

UR - http://www.scopus.com/inward/record.url?scp=34547786028&partnerID=8YFLogxK

U2 - 10.1109/TSM.2007.901408

DO - 10.1109/TSM.2007.901408

M3 - Article

AN - SCOPUS:34547786028

SN - 0894-6507

VL - 20

SP - 313

EP - 321

JO - IEEE Transactions on Semiconductor Manufacturing

JF - IEEE Transactions on Semiconductor Manufacturing

IS - 3

ER -

Halo and LDD engineering for multiple vTH high performance analog CMOS devices

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