Halo and LDD engineering for multiple vTH high performance analog CMOS devices

Jyh-Chyurn Guo*

*此作品的通信作者

    研究成果: Article同行評審

    4 引文 斯高帕斯(Scopus)

    摘要

    High performance analog (HPA) CMOS devices with multiple threshold voltages have been successfully fabricated in a 0.13-μm logic-based mixed-signal CMOS process on a single chip. The HPA devices demonstrate superior drivability, dc gain, matching, and reliability using an optimized halo and lightly doped drain (LLD) engineering approach combined with a unique dual gate oxide module for aggressive gate oxide thickness scaling.

    原文English
    頁(從 - 到)313-321
    頁數9
    期刊IEEE Transactions on Semiconductor Manufacturing
    20
    發行號3
    DOIs
    出版狀態Published - 1 8月 2007

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