Grain boundary trap-induced current transient in a 3-D NAND flash cell string

Wei Liang Lin*, Wen Jer Tsai, C. C. Cheng, S. H. Ku, Lenvis Liu, S. W. Hwang, Tao Cheng Lu, Kuang Chao Chen, Tseung-Yuen Tseng, Chih Yuan Lu

*此作品的通信作者

研究成果: Article同行評審

7 引文 斯高帕斯(Scopus)

摘要

Transient cell current caused by the trapping/detrapping of grain boundary traps in the polycrystalline silicon (poly-Si) channel of a 3-D NAND cell string is comprehensively studied in this paper. This transient has a time constant of 10 μs or longer and is strongly dependent on the bias history. It is also affected by the trap distribution as revealed by TCAD simulations. Sensing offset between program verify and read results in 'pseudo' charge loss/gain that reduces the sensing margin. The posttreatment of the poly-Si channel is suggested to mitigate this effect.

原文English
文章編號8666060
頁(從 - 到)1734-1740
頁數7
期刊IEEE Transactions on Electron Devices
66
發行號4
DOIs
出版狀態Published - 1 4月 2019

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