Generating Layouts of Standard Cells by Implicit Learning on Design Rules for Advanced Processes

For the advanced process technologies (e.g, finFET with EUV), the design rules (DRs) are the most challenging issue to the generation of cell layouts and all DR violations must be solved in a legal cell layout. However, most of previous works apply explicit encoding on the selected DRs into the routing engine and cannot accommodate the rapid growth on the size and complexity of DRs as the processes continue to advance. Therefore, in this paper, we propose two implicit-learning techniques, (1) experience-guidance learning (EGL) and (2) constraint-driven learning (CDL) for effectively solving such two problems of DRs, and meanwhile develop an automatic cell-layout generation (ACLG) framework for efficiently generating legal cell layouts. The experimental results show that in a finFET-EUV process [1], EGL and CDL successfully reduce all DR violations on eight target cells where each case takes averagely three minutes. As a result, without manual effort, ACLG is capable of generating legal layouts of standard cells by implicit learning on DRs of advanced processes.