General approach to design VLSI arrays for the multi-dimensional discrete Hartley transform

In this paper, a general memory-based approach to design VLSI arrays for the multi-dimensional (M-D) discrete Hartley transform (DHT) with any length is proposed. There are four parts of this approach: (1) a new M-D DHT formulation, (2) cyclic convolution representation, (3) systolic array realization, and (4) memory-based implementation. Deriving a new M-D DHT formulation avoids the undesirable overhead required in formal designs [1, 2, 3, 4]. Taking cyclic convolution provides high computing parallelism and low computation complexity. Using systolic array realization results in high computing speeds and low I/O cost. Adopting the memory-based implementation yields low hardware cost and low power dissipation. In summary, the proposed approach will lead to efficient and high-performance VLSI array designs for the M-D DHT.