Ge GAA FETs and TMD FinFETs for the applications beyond Si- A review

Two parts of work are included in this paper. In the first part, the novel Ge gate-all-around field effect transistors (GAA FETs) are introduced and discussed. Fabrication of Ge GAA FETs requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. First, a novel process to etch away the defective Ge near Ge/Si interface from epitaxial Ge grown on SOI achieves a nearly defect-free channel, good gate control triangular gate, larger effective width than rectangular fin, and have low punch-through current through the Si substrate. By dislocation removal, the defect-free Ge channel can be formed on nothing. The p-channel triangular Ge GAA FET with fin width (W_fin) of 52 nm and Lg of 183 nm has I_on/I_off = 10⁵, SS = 130 mV/dec, and I_on = 235 μA/μm at -1 V. Next, due to the highest electron mobility (2200 cm²/Vs) on (111) Ge surface, the n-channel triangular Ge GAA FET with (111) sidewalls on Si and Lg = 350 nm shows 2 times enhanced I_on with respect to the devices with near (110) sidewalls. Electrostatic control of SS = 94 mV/dec (at 1 V) can be further improved if superior gate stack than EOT = 5.5 nm and Dit = 1×10¹² cm^-2eV^-1 is used. The I_on can be further enhanced if the line edge roughness (LER) can be reduced. Second, a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge GAA FET with four {111} facets is also reviewed. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl₂/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, and nearly defectfree suspended channel, nFET and pFET with excellent performance have been demonstrated, including an I_on/I_off ratio exceeding 10⁸, the highest ever reported for Ge-based pFETs. The TMD FinFET devices are reviewed in the second part of this paper. The TMD FinFET channel is deposited by CVD. MoS₂ covered on Si fin and nanowire resulted in improved (+25%) I_on of the FinFET and nanowire FET. The PFETs also operated effectively and the N/P device V_th are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics. Furthermore, a 4 nm thin transitionmetal dichalcogenide (TMD) body FinFET with back gate control is also proposed and reviewed. Hydrogen plasma treatment of TMD is employed to lower the series resistance. The 2 nm thin back gate oxide enables 0.5 V of V_th shift with 1.2 V change in back bias for correcting device variations and dynamically configuring a device as a high performance or low leakage device. TMD can potentially provide sub-nm thin monolayer body needed for 2 nm node FinFET.