Ge FinFET CMOS Inverters with Improved Channel Surface Roughness by Using In-situ ALD Digital O3 Treatment

M. S. Yeh; G. L. Luo; F. J. Hou; P. J. Sung; C. J. Wang; C. J. Su; C. T. Wu; Y. C. Huang; T. C. Hong; Tien-Sheng Chao; B. Y. Chen; K. M. Chen; M. Izawa; M. Miura; M. Morimoto; H. Ishimura; Y. J. Lee; W. F. Wu; W. K. Yeh

doi:10.1109/EDTM.2018.8421457

Ge FinFET CMOS Inverters with Improved Channel Surface Roughness by Using In-situ ALD Digital O₃ Treatment

M. S. Yeh, G. L. Luo, F. J. Hou, P. J. Sung, C. J. Wang, C. J. Su, C. T. Wu, Y. C. Huang, T. C. Hong, Tien-Sheng Chao, B. Y. Chen, K. M. Chen, M. Izawa, M. Miura, M. Morimoto, H. Ishimura, Y. J. Lee, W. F. Wu, W. K. Yeh

研究成果: Conference contribution › 同行評審

6 引文斯高帕斯（Scopus）

摘要

Improved electrical characteristics of CMOS inverters composed of Ge n- and p-finFETs were demonstrated by utilizing newly introduced Ge surface treatments. In-situ ALD digital O₃ treatment was adopted on the surface of Ge fin sidewall in order to reduce the roughness and etching damages through the GeO desorption mechanism. By combining this treatment with optimized microwave annealing (MWA), SS and the I_ON/I_OFF ratio were remarkably improved in both n-finFET and p-finFET, and Ge CMOS inverters with high voltage gain of 50.3 V/V at low VD=0.6 V was realized.

原文	English
主出版物標題	2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	205-207
頁數	3
ISBN（列印）	9781538637111
DOIs	https://doi.org/10.1109/EDTM.2018.8421457
出版狀態	Published - 26 7月 2018
事件	2nd IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Kobe, Japan 持續時間: 13 3月 2018 → 16 3月 2018

出版系列

名字	2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings

Conference

Conference	2nd IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018
國家/地區	Japan
城市	Kobe
期間	13/03/18 → 16/03/18

存取文件

10.1109/EDTM.2018.8421457

其它文件與鏈接

Link to publication in Scopus

引用此

Yeh, M. S., Luo, G. L., Hou, F. J., Sung, P. J., Wang, C. J., Su, C. J., Wu, C. T., Huang, Y. C., Hong, T. C., Chao, T-S., Chen, B. Y., Chen, K. M., Izawa, M., Miura, M., Morimoto, M., Ishimura, H., Lee, Y. J., Wu, W. F., & Yeh, W. K. (2018). Ge FinFET CMOS Inverters with Improved Channel Surface Roughness by Using In-situ ALD Digital O₃ Treatment. 於 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings (頁 205-207). [8421457] (2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDTM.2018.8421457

Yeh, M. S. ; Luo, G. L. ; Hou, F. J. 等. / Ge FinFET CMOS Inverters with Improved Channel Surface Roughness by Using In-situ ALD Digital O₃ Treatment. 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. 頁 205-207 (2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings).

@inproceedings{8f8f63378021471c86ef712b10e71461,

title = "Ge FinFET CMOS Inverters with Improved Channel Surface Roughness by Using In-situ ALD Digital O3 Treatment",

abstract = "Improved electrical characteristics of CMOS inverters composed of Ge n- and p-finFETs were demonstrated by utilizing newly introduced Ge surface treatments. In-situ ALD digital O3 treatment was adopted on the surface of Ge fin sidewall in order to reduce the roughness and etching damages through the GeO desorption mechanism. By combining this treatment with optimized microwave annealing (MWA), SS and the ION/IOFF ratio were remarkably improved in both n-finFET and p-finFET, and Ge CMOS inverters with high voltage gain of 50.3 V/V at low VD=0.6 V was realized.",

keywords = "ALD, CMOS, FinFET, Ge, SS, and MWA",

author = "Yeh, {M. S.} and Luo, {G. L.} and Hou, {F. J.} and Sung, {P. J.} and Wang, {C. J.} and Su, {C. J.} and Wu, {C. T.} and Huang, {Y. C.} and Hong, {T. C.} and Tien-Sheng Chao and Chen, {B. Y.} and Chen, {K. M.} and M. Izawa and M. Miura and M. Morimoto and H. Ishimura and Lee, {Y. J.} and Wu, {W. F.} and Yeh, {W. K.}",

year = "2018",

month = jul,

day = "26",

doi = "10.1109/EDTM.2018.8421457",

language = "English",

isbn = "9781538637111",

series = "2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "205--207",

booktitle = "2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings",

address = "United States",

note = "null ; Conference date: 13-03-2018 Through 16-03-2018",

}

Yeh, MS, Luo, GL, Hou, FJ, Sung, PJ, Wang, CJ, Su, CJ, Wu, CT, Huang, YC, Hong, TC, Chao, T-S, Chen, BY, Chen, KM, Izawa, M, Miura, M, Morimoto, M, Ishimura, H, Lee, YJ, Wu, WF & Yeh, WK 2018, Ge FinFET CMOS Inverters with Improved Channel Surface Roughness by Using In-situ ALD Digital O₃ Treatment. 於 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings., 8421457, 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 頁 205-207, 2nd IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018, Kobe, Japan, 13/03/18. https://doi.org/10.1109/EDTM.2018.8421457

Ge FinFET CMOS Inverters with Improved Channel Surface Roughness by Using In-situ ALD Digital O₃ Treatment. / Yeh, M. S.; Luo, G. L.; Hou, F. J. 等.

2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 205-207 8421457 (2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Ge FinFET CMOS Inverters with Improved Channel Surface Roughness by Using In-situ ALD Digital O3 Treatment

AU - Yeh, M. S.

AU - Luo, G. L.

AU - Hou, F. J.

AU - Sung, P. J.

AU - Wang, C. J.

AU - Su, C. J.

AU - Wu, C. T.

AU - Huang, Y. C.

AU - Hong, T. C.

AU - Chao, Tien-Sheng

AU - Chen, B. Y.

AU - Chen, K. M.

AU - Izawa, M.

AU - Miura, M.

AU - Morimoto, M.

AU - Ishimura, H.

AU - Lee, Y. J.

AU - Wu, W. F.

AU - Yeh, W. K.

PY - 2018/7/26

Y1 - 2018/7/26

N2 - Improved electrical characteristics of CMOS inverters composed of Ge n- and p-finFETs were demonstrated by utilizing newly introduced Ge surface treatments. In-situ ALD digital O3 treatment was adopted on the surface of Ge fin sidewall in order to reduce the roughness and etching damages through the GeO desorption mechanism. By combining this treatment with optimized microwave annealing (MWA), SS and the ION/IOFF ratio were remarkably improved in both n-finFET and p-finFET, and Ge CMOS inverters with high voltage gain of 50.3 V/V at low VD=0.6 V was realized.

AB - Improved electrical characteristics of CMOS inverters composed of Ge n- and p-finFETs were demonstrated by utilizing newly introduced Ge surface treatments. In-situ ALD digital O3 treatment was adopted on the surface of Ge fin sidewall in order to reduce the roughness and etching damages through the GeO desorption mechanism. By combining this treatment with optimized microwave annealing (MWA), SS and the ION/IOFF ratio were remarkably improved in both n-finFET and p-finFET, and Ge CMOS inverters with high voltage gain of 50.3 V/V at low VD=0.6 V was realized.

KW - ALD

KW - CMOS

KW - FinFET

KW - Ge

KW - SS

KW - and MWA

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U2 - 10.1109/EDTM.2018.8421457

DO - 10.1109/EDTM.2018.8421457

M3 - Conference contribution

AN - SCOPUS:85051499668

SN - 9781538637111

T3 - 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings

SP - 205

EP - 207

BT - 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 13 March 2018 through 16 March 2018

ER -

Yeh MS, Luo GL, Hou FJ, Sung PJ, Wang CJ, Su CJ 等. Ge FinFET CMOS Inverters with Improved Channel Surface Roughness by Using In-situ ALD Digital O₃ Treatment. 於 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 205-207. 8421457. (2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings). doi: 10.1109/EDTM.2018.8421457