Gate-stack engineering for self-organized Ge-dot/SiO 2 /SiGe-shell MOS capacitors

Wei Ting Lai, Kuo Ching Yang, Po Hsiang Liao, Tom George, Pei-Wen Li*


研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)


We report the first-of-its-kind, self-organized gate-stack heterostructure of Ge-dot/SiO 2 /SiGe-shell on Si fabricated in a single step through the selective oxidation of a SiGe-nanopatterned pillar over a Si 3 N 4 buffer layer on a Si substrate. Process-controlled tunability of the Ge-dot size (7.5–90 nm), the SiO 2 thickness (3–4 nm), and the SiGe-shell thickness (2–15 nm) have been demonstrated, enabling a practically achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices. Detailed morphologies, structural, and electrical interfacial properties of the SiO 2 /Ge-dot and SiO 2 /SiGe interfaces were assessed using transmission electron microscopy, energy dispersive X-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Notably, NiGe/SiO 2 /SiGe and Al/SiO 2 /Ge-dot/SiO 2 /SiGe MOS capacitors exhibit low interface trap densities of as low as 3–5 × 10 11 cm −2 eV −1 and fixed charge densities of 1–5 × 10 11 cm −2 , suggesting good-quality SiO 2 /SiGe-shell and SiO 2 /Ge-dot interfaces. In addition, the advantage of having single-crystalline Si 1− x Ge x shell (x > 0.5) in a compressive stress state in our self-aligned gate-stack heterostructure has great promise for possible SiGe (or Ge) MOS nanoelectronic and nanophotonic applications.

期刊Frontiers in Materials
出版狀態Published - 11 2月 2016


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