Gate dielectric material and process effects on distribution pattern of nano-resistors in solid-state incandescent light emitting devices

Since the solid-state incandescent light emitting device is formed from the dielectric breakdown of the MOS capacitor, the gate dielectric layer is critical to the light emitting phenomena. In this paper, influences of the high-k gate dielectric material and process condition on the distribution of nano-resistors in the solid-state incandescent light emitting device are investigated. The post deposition temperature affects the gate dielectric property and the formation of nano-resistors. The gate dielectric deposition time determines its thickness and the length of the nano-resistor. In addition, the embedding of a high emissivity WO_x layer in the gate dielectric induces defects in the gate dielectric layer. These factors influence the mechanism of the dielectric breakdown process and therefore, the pattern and size of the bright dots during the light emitting process. Graphical abstract: [Figure not available: see fulltext.]