Gate capacitance modeling and diameter-dependent performance of nanowire MOSFETs

Yeonghun Lee*, Kuniyuki Kakushima, Kenji Natori, Hiroshi Iwai

*此作品的通信作者

研究成果: Article同行評審

18 引文 斯高帕斯(Scopus)

摘要

We investigated the diameter-dependent performance of Si and InAs nanowire metal-oxide-semiconductor field-effect transistors (NW MOSFETs) by developing a gate capacitance model. A nonparabolic effective-mass approximation and a semiclassical ballistic transport model were used. The capacitance model helped interpret the different contributions of the capacitances, which were due to the inversion-layer centroid and density of states. As a result, the inversion-layer centroid was close to the surface with a shrinking diameter. In Si NWs, this effect increased the gate capacitance in a small diameter. On the other hand, in InAs NWs, the density of states could decrease the gate capacitance in a small diameter. In both NWs, the on-current drastically increased in diameter smaller than 5 nm mainly due to the increase in the gate capacitance. The diameter-dependent injection velocity reached a peak around 5 nm in both NWs. Our results could imply that the peak in the diameter-dependent injection velocity is a universal feature of NW MOSFETs. With respect to intrinsic gate delay, the highest injection velocity led to the best performance of Si NWs; however, this case was not accompanied with the best performance of InAs NWs.

原文English
文章編號6152143
頁(從 - 到)1037-1045
頁數9
期刊IEEE Transactions on Electron Devices
59
發行號4
DOIs
出版狀態Published - 四月 2012

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