Future Computing Platform Design: A Cross-Layer Design Approach

Hsiang Yun Cheng, Chun Feng Wu, Christian Hakert, Kuan Hsun Chen, Yuan Hao Chang, Jian Jia Chen, Chia Lin Yang, Tei Wei Kuo

研究成果: Conference contribution同行評審

7 引文 斯高帕斯(Scopus)

摘要

Future computing platforms are facing a paradigm shift with the emerging resistive memory technologies. First, they offer fast memory accesses and data persistence in a single large-capacity device deployed on the memory bus, blurring the boundary between memory and storage. Second, they enable computing-in-memory for neuromorphic computing to mitigate costly data movements. Due to the non-ideality of these resistive memory devices at the moment, we envision that cross-layer design is essential to bring such a system into practice. In this paper, we showcase a few examples to demonstrate how cross-layer design can be developed to fully exploit the potential of resistive memories and accelerate its adoption for future computing platforms.

原文English
主出版物標題Proceedings of the 2021 Design, Automation and Test in Europe, DATE 2021
發行者Institute of Electrical and Electronics Engineers Inc.
頁面312-317
頁數6
ISBN(電子)9783981926354
DOIs
出版狀態Published - 1 2月 2021
事件2021 Design, Automation and Test in Europe Conference and Exhibition, DATE 2021 - Virtual, Online
持續時間: 1 2月 20215 2月 2021

出版系列

名字Proceedings -Design, Automation and Test in Europe, DATE
2021-February
ISSN(列印)1530-1591

Conference

Conference2021 Design, Automation and Test in Europe Conference and Exhibition, DATE 2021
城市Virtual, Online
期間1/02/215/02/21

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