Functional Verification

Hung Pin Wen*, Li C. Wang, Kwang Ting Cheng

*此作品的通信作者

研究成果: Chapter同行評審

1 引文 斯高帕斯(Scopus)

摘要

This chapter reviews the basic concepts of functional verification and the challenges associated with it. In a typical integrated circuit design flow, functional verification ensures that the implementation conforms to the specification. Because of the rapid growth of both design size and complexity, functional verification has become one of the key bottlenecks in the design process. Different levels of the verification hierarchy, including the designer level, unit level, core level, chip level, and system/board level, are explained. Various coverage metrics used for measuring the explored extent of verification also are provided. The simulation-based approach is currently the most pervasive form of verification. Key components such as test bench and simulation environment development are reviewed as well. The emerging assertion-based verification method is explained in detail. To compensate for the incompleteness of simulation-based verification, formal methods built on mathematical theories are developed. Basic concepts in equivalence checking, model checking, and theorem proving also are reviewed in the chapter. Current research efforts toward advancing functional verification are summarized in the conclusion.

原文English
主出版物標題Electronic Design Automation
發行者Elsevier Inc.
頁面513-573
頁數61
ISBN(列印)9780123743640
DOIs
出版狀態Published - 1 12月 2009

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