Full-custom all-digital phase locked loop for clock generation

Mu Lee Huang, Chung-Chih Hung

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

A novel approach of constructing an All-Digital Phase Locked Loop (ADPLL) is presented in this paper. A 3-Step symmetric Time-to-Digital Converter (TDC) is proposed with both long dynamic range and high resolution. The Upper-and-Lower-boundaries-Cut-off-Determination (ULCD) logic is presented for a full-custom digital loop filter. With this method, an all-digital PLL can be designed without synthesis procedures. The Digitally-Controlled Oscillator is designed by ring architecture with periodic variation linear. The dynamic range of the TDC is 7.7 ns and the finest resolution of the TDC is only 12.7 ps. System locked time is only 1.62 us. The rms jitter and P-P jitter is 4.68 ps and 38.68 ps in the measurement results. And the power dissipation is only 7.55 mW.

原文English
主出版物標題2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781479962754
DOIs
出版狀態Published - 28 5月 2015
事件2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan
持續時間: 27 4月 201529 4月 2015

出版系列

名字2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Conference

Conference2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
國家/地區Taiwan
城市Hsinchu
期間27/04/1529/04/15

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