Full current-mode techniques for high-speed CMOS SRAMs

S. M. Wang; Chung-Yu Wu

doi:10.1109/ISCAS.2002.1010522

Full current-mode techniques for high-speed CMOS SRAMs

S. M. Wang^*, Chung-Yu Wu

^*此作品的通信作者

研究成果: Conference article › 同行評審

4 引文斯高帕斯（Scopus）

摘要

This paper describes an experimental 32K×8 CMOS SRAM with a 9ns access time at a supply voltage of 3V using a 0.35um 1P2M CMOS logic technology. Based on the full current-mode techniques for read/write operation, the sensing speed and write pulse width are insensitive to the bit-line capacitance. Due to these techniques, the voltage swing at the bit-line and data-line can be kept quite small all the time. The active current is 28mA at 100MHz under typical conditions.

原文	English
頁（從 - 到）	IV/580-IV/582
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	4
DOIs	https://doi.org/10.1109/ISCAS.2002.1010522
出版狀態	Published - 2002
事件	2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, 美國持續時間: 26 5月 2002 → 29 5月 2002

存取文件

10.1109/ISCAS.2002.1010522

其它文件與鏈接

Link to publication in Scopus

引用此

@article{9b840384d07440bd99ddcf85d57972a1,

title = "Full current-mode techniques for high-speed CMOS SRAMs",

abstract = "This paper describes an experimental 32K×8 CMOS SRAM with a 9ns access time at a supply voltage of 3V using a 0.35um 1P2M CMOS logic technology. Based on the full current-mode techniques for read/write operation, the sensing speed and write pulse width are insensitive to the bit-line capacitance. Due to these techniques, the voltage swing at the bit-line and data-line can be kept quite small all the time. The active current is 28mA at 100MHz under typical conditions.",

author = "Wang, {S. M.} and Chung-Yu Wu",

year = "2002",

doi = "10.1109/ISCAS.2002.1010522",

language = "English",

volume = "4",

pages = "IV/580--IV/582",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2002 IEEE International Symposium on Circuits and Systems ; Conference date: 26-05-2002 Through 29-05-2002",

}

TY - JOUR

T1 - Full current-mode techniques for high-speed CMOS SRAMs

AU - Wang, S. M.

AU - Wu, Chung-Yu

PY - 2002

Y1 - 2002

N2 - This paper describes an experimental 32K×8 CMOS SRAM with a 9ns access time at a supply voltage of 3V using a 0.35um 1P2M CMOS logic technology. Based on the full current-mode techniques for read/write operation, the sensing speed and write pulse width are insensitive to the bit-line capacitance. Due to these techniques, the voltage swing at the bit-line and data-line can be kept quite small all the time. The active current is 28mA at 100MHz under typical conditions.

AB - This paper describes an experimental 32K×8 CMOS SRAM with a 9ns access time at a supply voltage of 3V using a 0.35um 1P2M CMOS logic technology. Based on the full current-mode techniques for read/write operation, the sensing speed and write pulse width are insensitive to the bit-line capacitance. Due to these techniques, the voltage swing at the bit-line and data-line can be kept quite small all the time. The active current is 28mA at 100MHz under typical conditions.

UR - http://www.scopus.com/inward/record.url?scp=0036290714&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2002.1010522

DO - 10.1109/ISCAS.2002.1010522

M3 - Conference article

AN - SCOPUS:0036290714

SN - 0271-4310

VL - 4

SP - IV/580-IV/582

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2002 IEEE International Symposium on Circuits and Systems

Y2 - 26 May 2002 through 29 May 2002

ER -

Full current-mode techniques for high-speed CMOS SRAMs

摘要

存取文件

其它文件與鏈接

指紋

引用此