Full current-mode techniques for high-speed CMOS SRAMs

S. M. Wang*, Chung-Yu Wu

*此作品的通信作者

    研究成果: Conference article同行評審

    4 引文 斯高帕斯(Scopus)

    摘要

    This paper describes an experimental 32K×8 CMOS SRAM with a 9ns access time at a supply voltage of 3V using a 0.35um 1P2M CMOS logic technology. Based on the full current-mode techniques for read/write operation, the sensing speed and write pulse width are insensitive to the bit-line capacitance. Due to these techniques, the voltage swing at the bit-line and data-line can be kept quite small all the time. The active current is 28mA at 100MHz under typical conditions.

    原文English
    頁(從 - 到)IV/580-IV/582
    期刊Proceedings - IEEE International Symposium on Circuits and Systems
    4
    DOIs
    出版狀態Published - 2002
    事件2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States
    持續時間: 26 5月 200229 5月 2002

    指紋

    深入研究「Full current-mode techniques for high-speed CMOS SRAMs」主題。共同形成了獨特的指紋。

    引用此