Full-chip thermal analysis for the early design stage via generalized integral transforms

Pei Yu Huang*, Chih Kang Lin, Yu-Min Lee

*此作品的通信作者

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

The capability of predicting the temperature profile is critically important for circuit timing estimation, leakage reduction, power estimation, hotspot avoidance, and reliability concerns during modern IC designs. This paper presents an accurate and fast analytical full-chip thermal simulator for the early-stage temperature-aware chip design. By using the technique of generalized integral transforms (GIT), our proposed method can accurately estimate the temperature distribution of full-chip with very small truncation points of bases in the spatial domain. We also develop a fast Fourier transform (FFT) like evaluating algorithm to efficiently evaluate the temperature distribution. Experimental results confirm that our GIT based analyzer can achieve an order of magnitude speedup compared with a highly efficient Green's function based method.

原文English
主出版物標題2008 Asia and South Pacific Design Automation Conference, ASP-DAC
頁面462-467
頁數6
DOIs
出版狀態Published - 2008
事件2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul, Korea, Republic of
持續時間: 21 3月 200824 3月 2008

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2008 Asia and South Pacific Design Automation Conference, ASP-DAC
國家/地區Korea, Republic of
城市Seoul
期間21/03/0824/03/08

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