Flash memory scaling: From material selection to performance improvement

Tuo-Hung Hou*, Jaegoo Lee, Jonathan T. Shaw, Edwin C. Kan

*此作品的通信作者

    研究成果: Conference contribution同行評審

    3 引文 斯高帕斯(Scopus)

    摘要

    Below the 65-nm technology node, scaling of Flash memory, NAND, NOR or embedded, needs smart and heterogeneous integration of materials in the entire device structure. In addition to maintaining retention, in the order of importance, we need to continuously make functional density (bits/cm 2) higher, cycling endurance longer, program/erase (P/E) voltage lower (negated by the read disturbance, multi-level possibility and noise margin), and P/E time faster (helped by inserting SRAM buffer at system interface). From both theory and experiments, we will compare the advantages and disadvantages in various material choices in view of 3D electrostatics, quantum transport and CMOS process compatibility.

    原文English
    主出版物標題Materials Research Society Symposium Proceedings - Materials Science and Technology for Nonvolatile Memories
    頁面3-15
    頁數13
    DOIs
    出版狀態Published - 3月 2008
    事件Materials Science and Technology for Nonvolatile Memories - San Francisco, CA, United States
    持續時間: 24 3月 200827 3月 2008

    出版系列

    名字Materials Research Society Symposium Proceedings
    1071
    ISSN(列印)0272-9172

    Conference

    ConferenceMaterials Science and Technology for Nonvolatile Memories
    國家/地區United States
    城市San Francisco, CA
    期間24/03/0827/03/08

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