Fixed-width multiplier for DSP application

Shyh-Jye Jou; Hui Hsuan Wang

doi:10.1109/ICCD.2000.878302

Fixed-width multiplier for DSP application

Shyh-Jye Jou^*, Hui Hsuan Wang

^*此作品的通信作者

電子研究所

研究成果: Paper › 同行評審

38 引文斯高帕斯（Scopus）

摘要

A new compensation method that reduce the error of fixed-width multiplier for digital signal processing (DSP) application is proposed. The designs of using this input-number based compensation method are carried out on array multiplier and Booth multiplier. The hardware complexity is reduced to about 50% of the original multiplier. Design results show that the new architectures have lower hardware overhead, lower error and fast operation speed as compared with other proposed architectures.

原文	English
頁面	318-322
頁數	5
DOIs	https://doi.org/10.1109/ICCD.2000.878302
出版狀態	Published - 1 1月 2000
事件	2000 International Conference on Computer Design - Austin, TX, USA 持續時間: 17 9月 2000 → 20 9月 2000

Conference

Conference	2000 International Conference on Computer Design
城市	Austin, TX, USA
期間	17/09/00 → 20/09/00

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10.1109/ICCD.2000.878302

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引用此

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title = "Fixed-width multiplier for DSP application",

abstract = "A new compensation method that reduce the error of fixed-width multiplier for digital signal processing (DSP) application is proposed. The designs of using this input-number based compensation method are carried out on array multiplier and Booth multiplier. The hardware complexity is reduced to about 50% of the original multiplier. Design results show that the new architectures have lower hardware overhead, lower error and fast operation speed as compared with other proposed architectures.",

author = "Shyh-Jye Jou and Wang, {Hui Hsuan}",

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AU - Wang, Hui Hsuan

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N2 - A new compensation method that reduce the error of fixed-width multiplier for digital signal processing (DSP) application is proposed. The designs of using this input-number based compensation method are carried out on array multiplier and Booth multiplier. The hardware complexity is reduced to about 50% of the original multiplier. Design results show that the new architectures have lower hardware overhead, lower error and fast operation speed as compared with other proposed architectures.

AB - A new compensation method that reduce the error of fixed-width multiplier for digital signal processing (DSP) application is proposed. The designs of using this input-number based compensation method are carried out on array multiplier and Booth multiplier. The hardware complexity is reduced to about 50% of the original multiplier. Design results show that the new architectures have lower hardware overhead, lower error and fast operation speed as compared with other proposed architectures.

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DO - 10.1109/ICCD.2000.878302

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T2 - 2000 International Conference on Computer Design

Y2 - 17 September 2000 through 20 September 2000

ER -

Fixed-width multiplier for DSP application

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