First Integration of 10-V CMOS Logic Circuit, 20-V Gate Driver, and 600-V VDMOSFET on a 4H-SiC Single Chip

B. Y. Tsui*, C. L. Hung, T. K. Tsai, Y. C. Tsui, T. W. Wang, Y. X. Wen, C. P. Shih, J. C. Wang, L. J. Lin, C. H. Wang, K. W. Chu, Po-Hung Chen

*此作品的通信作者

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

In this work, we reported the integration of 10-V CMOS logic circuit, 20-V gate driver, and 600-V VDMOSFET on a 4H-SiC single chip for full SiC smart power ICs. This integration process features PMOSFET isolation (P-iso) from the high voltage substrate, local oxidation of SiC isolation between devices, dual gate oxide thickness, and P+ poly-Si gate. It is demonstrated that the blocking capability of the P-iso structure can exceed 700 V and the switch of the VDMOSFET can be controlled by a 10-V signal through a 10-V to 20-V level shifter and a 20-V gate driver.

原文English
主出版物標題2022 34th International Symposium on Power Semiconductor Devices and ICs, ISPSD 2022
發行者Institute of Electrical and Electronics Engineers Inc.
頁面321-324
頁數4
ISBN(電子)9781665422017
DOIs
出版狀態Published - 2022
事件34th IEEE International Symposium on Power Semiconductor Devices and ICs, ISPSD 2022 - Vancouver, Canada
持續時間: 22 5月 202225 5月 2022

出版系列

名字Proceedings of the International Symposium on Power Semiconductor Devices and ICs
2022-May
ISSN(列印)1063-6854

Conference

Conference34th IEEE International Symposium on Power Semiconductor Devices and ICs, ISPSD 2022
國家/地區Canada
城市Vancouver
期間22/05/2225/05/22

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