First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications

Shu Wei Chang, Tsung Han Lu, Cong Yi Yang, Cheng Jui Yeh, Min Kun Huang, Ching Fan Meng, Po Jen Chen, Ting Hsuan Chang, Yan Shiuan Chang, Jhe Wei Jhu, Tzu Chieh Hong, Chu Chu Ke, Xin Ren Yu, Wen Hsiang Lu, Mohammed Aftab Baig, Ta Chun Cho, Po Jung Sung, Chun Jung Su, Fu Kuo Hsueh, Bo Yuan ChenHsin Hui Hu, Chien Ting Wu, Kun Lin Lin, William Cheng Yu Ma, Darsen D. Lu, Kuo Hsing Kao, Yao Jen Lee, Cheng Li Lin, Kun Ping Huang, Kun Ming Chen, Yiming Li, Seiji Samukawa, Tien Sheng Chao, Guo Wei Huang, Wen Fa Wu, Wen Hsi Lee, Jiun Yun Li, Jia Min Shieh, Jenn Hwan Tarng, Yeong Her Wang, Wen Kuan Yeh

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

In this article, heterogeneous complementary field-effect-transistor (CFET) constructed by vertically stacking amorphous indium gallium zinc oxide (a-IGZO) n-channel on poly-Si p-channel with their own dielectric layer and work function metal gate inverters were demonstrated. Meanwhile, high-frequency IGZO radio frequency (RF) devices with poly-Si as guard ring material simultaneously were fabricated in the same process. High <formula> <tex>$f_{T}$</tex> </formula> and <formula> <tex>$f_{max}$</tex> </formula> IGZO Radio Frequency Integrated Circuits (RFICs) with the excellent on-off ratio need to be promoted by introducing fluorine-based gas. For the IGZO device in CFET, its threshold voltage can be tuned by the adjusted gate for ideal inverter operation at different supply voltage ( <formula> <tex>$V_{DD}$</tex> </formula> ). Moreover, the swing of the IGZO transistor and the gain extracted from voltage transfer characteristic (VTC) curves can also be improved when the controlled gate and adjusted gate are connected as an input terminal, but the <formula> <tex>$V_{TH}$</tex> </formula> tunability for the inverter is satisfied in the meantime. We also simulated 6T-SRAM circuit by SPICE model to further investigate the potential of an adjusted gate for optimizing the noise margin during SRAM operation.

原文English
頁(從 - 到)2101-2107
頁數7
期刊IEEE Transactions on Electron Devices
69
發行號4
DOIs
出版狀態Published - 1 4月 2022

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