@inproceedings{ce1e7acef2884abb97df28cc484f1269,
title = "First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications",
abstract = "For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.",
author = "Chang, {S. W.} and Li, {J. H.} and Huang, {M. K.} and Huang, {Y. C.} and Huang, {S. T.} and Wang, {H. C.} and Huang, {Y. J.} and Wang, {J. Y.} and Yu, {L. W.} and Huang, {Y. F.} and Hsueh, {F. K.} and Sung, {P. J.} and Wu, {C. T.} and Ma, {W. C.Y.} and Kao, {K. H.} and Lee, {Y. J.} and Lin, {C. L.} and Chuang, {R. W.} and Huang, {K. P.} and S. Samukawa and Y. Li and Lee, {W. H.} and Chu, {T. Y.} and Tien-Sheng Chao and Huang, {G. W.} and Wu, {W. F.} and Li, {J. Y.} and Shieh, {J. M.} and Yeh, {W. K.} and Wang, {Y. H.} and Lu, {D. D.} and Wang, {C. J.} and Lin, {N. C.} and Su, {C. J.} and Lo, {S. H.} and Huang, {H. F.}",
year = "2019",
month = dec,
doi = "10.1109/IEDM19573.2019.8993525",
language = "English",
series = "Technical Digest - International Electron Devices Meeting, IEDM",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2019 IEEE International Electron Devices Meeting, IEDM 2019",
address = "United States",
note = "null ; Conference date: 07-12-2019 Through 11-12-2019",
}