First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

S. W. Chang, J. H. Li, M. K. Huang, Y. C. Huang, S. T. Huang, H. C. Wang, Y. J. Huang, J. Y. Wang, L. W. Yu, Y. F. Huang, F. K. Hsueh, P. J. Sung*, C. T. Wu, W. C.Y. Ma, K. H. Kao, Y. J. Lee*, C. L. Lin, R. W. Chuang, K. P. Huang, S. SamukawaY. Li, W. H. Lee, T. Y. Chu, Tien-Sheng Chao, G. W. Huang, W. F. Wu, J. Y. Li, J. M. Shieh, W. K. Yeh, Y. H. Wang, D. D. Lu, C. J. Wang, N. C. Lin, C. J. Su, S. H. Lo, H. F. Huang

*此作品的通信作者

研究成果: Conference contribution同行評審

21 引文 斯高帕斯(Scopus)

摘要

For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.

原文English
主出版物標題2019 IEEE International Electron Devices Meeting, IEDM 2019
發行者Institute of Electrical and Electronics Engineers Inc.
頁數4
ISBN(電子)9781728140315
DOIs
出版狀態Published - 12月 2019
事件65th Annual IEEE International Electron Devices Meeting, IEDM 2019 - San Francisco, United States
持續時間: 7 12月 201911 12月 2019

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
2019-December
ISSN(列印)0163-1918

Conference

Conference65th Annual IEEE International Electron Devices Meeting, IEDM 2019
國家/地區United States
城市San Francisco
期間7/12/1911/12/19

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