First Demonstration of Annealing-Free Atomic-Layer-Deposited In2O3 Top-Gate Devices With Robust Positive/Negative Bias Temperature Instability

Li Cheng Teng; Yu Chieh Liao; Chi Cheng Tian; Chien Chun Chen; Yu Hsien Lin; Chao Hsin Chien

doi:10.1109/TED.2025.3648690

First Demonstration of Annealing-Free Atomic-Layer-Deposited In₂O₃ Top-Gate Devices With Robust Positive/Negative Bias Temperature Instability

Li Cheng Teng
, Yu Chieh Liao
, Chi Cheng Tian
, Chien Chun Chen
, Yu Hsien Lin
, Chao Hsin Chien^*

^*此作品的通信作者

研究成果: Article › 同行評審

摘要

In this work, we present the first demonstration of ultrathin In₂O₃ top-gate (TG) transistors with a short-channel length of 100 nm, fabricated using back-end-of-line (BEOL)-compatible processing (≤ 250 °C) and various TG oxide deposition techniques. Plasma-enhanced ZrO₂-based TG devices exhibit impressive performance, with I_{on, max} = 378µA/µm @ V_D = 1 V, a minimum subthreshold swing (SS) of 70 mV/dec, and a threshold voltage (V_t) shift of only 0.05 V under positive bias stress (V_G = V_t+2 V) for 10 000 s. Notably, these devices exhibit excellent switching behavior without needing post-deposition annealing, making them highly promising candidates for monolithic 3-D (M3D) integration.

原文	English
頁（從 - 到）	1381-1386
頁數	6
期刊	IEEE Transactions on Electron Devices
卷	73
發行號	3
DOIs	https://doi.org/10.1109/TED.2025.3648690
出版狀態	Published - 2026

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10.1109/TED.2025.3648690

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@article{268aeb9558084d5bb5a65e26d7dbd611,

title = "First Demonstration of Annealing-Free Atomic-Layer-Deposited In2O3 Top-Gate Devices With Robust Positive/Negative Bias Temperature Instability",

abstract = "In this work, we present the first demonstration of ultrathin In2O3 top-gate (TG) transistors with a short-channel length of 100 nm, fabricated using back-end-of-line (BEOL)-compatible processing (≤ 250 °C) and various TG oxide deposition techniques. Plasma-enhanced ZrO2-based TG devices exhibit impressive performance, with Ion, max = 378µA/µm @ VD = 1 V, a minimum subthreshold swing (SS) of 70 mV/dec, and a threshold voltage (Vt) shift of only 0.05 V under positive bias stress (VG = Vt+2 V) for 10 000 s. Notably, these devices exhibit excellent switching behavior without needing post-deposition annealing, making them highly promising candidates for monolithic 3-D (M3D) integration.",

keywords = "Back-end-of-line (BEOL), InO, monolithic 3-D (M3D) integration, positive/negative bias temperature instability (BTI), top-gate (TG) devices",

author = "Teng, \{Li Cheng\} and Liao, \{Yu Chieh\} and Tian, \{Chi Cheng\} and Chen, \{Chien Chun\} and Lin, \{Yu Hsien\} and Chien, \{Chao Hsin\}",

note = "Publisher Copyright: {\textcopyright} 1963-2012 IEEE.",

year = "2026",

doi = "10.1109/TED.2025.3648690",

language = "English",

volume = "73",

pages = "1381--1386",

journal = "IEEE Transactions on Electron Devices",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

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TY - JOUR

T1 - First Demonstration of Annealing-Free Atomic-Layer-Deposited In2O3 Top-Gate Devices With Robust Positive/Negative Bias Temperature Instability

AU - Teng, Li Cheng

AU - Liao, Yu Chieh

AU - Tian, Chi Cheng

AU - Chen, Chien Chun

AU - Lin, Yu Hsien

AU - Chien, Chao Hsin

PY - 2026

Y1 - 2026

N2 - In this work, we present the first demonstration of ultrathin In2O3 top-gate (TG) transistors with a short-channel length of 100 nm, fabricated using back-end-of-line (BEOL)-compatible processing (≤ 250 °C) and various TG oxide deposition techniques. Plasma-enhanced ZrO2-based TG devices exhibit impressive performance, with Ion, max = 378µA/µm @ VD = 1 V, a minimum subthreshold swing (SS) of 70 mV/dec, and a threshold voltage (Vt) shift of only 0.05 V under positive bias stress (VG = Vt+2 V) for 10 000 s. Notably, these devices exhibit excellent switching behavior without needing post-deposition annealing, making them highly promising candidates for monolithic 3-D (M3D) integration.

AB - In this work, we present the first demonstration of ultrathin In2O3 top-gate (TG) transistors with a short-channel length of 100 nm, fabricated using back-end-of-line (BEOL)-compatible processing (≤ 250 °C) and various TG oxide deposition techniques. Plasma-enhanced ZrO2-based TG devices exhibit impressive performance, with Ion, max = 378µA/µm @ VD = 1 V, a minimum subthreshold swing (SS) of 70 mV/dec, and a threshold voltage (Vt) shift of only 0.05 V under positive bias stress (VG = Vt+2 V) for 10 000 s. Notably, these devices exhibit excellent switching behavior without needing post-deposition annealing, making them highly promising candidates for monolithic 3-D (M3D) integration.

KW - Back-end-of-line (BEOL)

KW - InO

KW - monolithic 3-D (M3D) integration

KW - positive/negative bias temperature instability (BTI)

KW - top-gate (TG) devices

UR - https://www.scopus.com/pages/publications/105027004729

U2 - 10.1109/TED.2025.3648690

DO - 10.1109/TED.2025.3648690

M3 - Article

AN - SCOPUS:105027004729

SN - 0018-9383

VL - 73

SP - 1381

EP - 1386

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 3

ER -

First Demonstration of Annealing-Free Atomic-Layer-Deposited In2O3 Top-Gate Devices With Robust Positive/Negative Bias Temperature Instability

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First Demonstration of Annealing-Free Atomic-Layer-Deposited In₂O₃ Top-Gate Devices With Robust Positive/Negative Bias Temperature Instability