First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate

Chao Ching Cheng; Yun Yan Chung; Uing Yang Li; Chao Ting Lin; Chi Feng Li; Jyun Hong Chen; Tung Yen Lai; Kai Shin Li; Jia Min Shieh; Sheng Kai Su; Hung Li Chiang; Tzu Chiang Chen; Lain Jong Li; H. S.Philip Wong; Chao-Hsin Chien

doi:10.23919/VLSIT.2019.8776498

First demonstration of 40-nm channel length top-gate WS₂ pFET using channel area-selective CVD growth directly on SiO_x/Si substrate

Chao Ching Cheng, Yun Yan Chung, Uing Yang Li, Chao Ting Lin, Chi Feng Li, Jyun Hong Chen, Tung Yen Lai, Kai Shin Li, Jia Min Shieh, Sheng Kai Su, Hung Li Chiang, Tzu Chiang Chen, Lain Jong Li, H. S.Philip Wong, Chao-Hsin Chien^*

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

35 引文斯高帕斯（Scopus）

摘要

Area-selective channel material growth for 2D transistors is more desirable for volume manufacturing than exfoliation or wet/dry transfer after large area growth. We demonstrate the first top-gate WS₂ p-channel field-effect transistors (p-FETs) fabricated on SiOx/Si substrate using channel area-selective CVD growth. Smooth and uniform WS₂ comprising approximately 6 layers was formed by area-selective CVD growth in which a patterned tungsten-source/drain served as the seed for WS₂ growth. For a 40 nm gate length transistor, the device has impressive electrical characteristics: on/off ratio of 106, a S.S. of 97 mV/dec., and nearly zero DIBL.

原文	English
主出版物標題	2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	T244-T245
頁數	2
ISBN（電子）	9784863487178
DOIs	https://doi.org/10.23919/VLSIT.2019.8776498
出版狀態	Published - 6月 2019
事件	39th Symposium on VLSI Technology, VLSI Technology 2019 - Kyoto, 日本持續時間: 9 6月 2019 → 14 6月 2019

出版系列

名字	Digest of Technical Papers - Symposium on VLSI Technology
卷	2019-June
ISSN（列印）	0743-1562

Conference

Conference	39th Symposium on VLSI Technology, VLSI Technology 2019
國家/地區	日本
城市	Kyoto
期間	9/06/19 → 14/06/19

存取文件

10.23919/VLSIT.2019.8776498

其它文件與鏈接

Link to publication in Scopus

引用此

Cheng, C. C., Chung, Y. Y., Li, U. Y., Lin, C. T., Li, C. F., Chen, J. H., Lai, T. Y., Li, K. S., Shieh, J. M., Su, S. K., Chiang, H. L., Chen, T. C., Li, L. J., Wong, H. S. P., & Chien, C.-H. (2019). First demonstration of 40-nm channel length top-gate WS₂ pFET using channel area-selective CVD growth directly on SiO_x/Si substrate. 於 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers (頁 T244-T245). 文章 8776498 (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIT.2019.8776498

Cheng, Chao Ching ; Chung, Yun Yan ; Li, Uing Yang 等. / First demonstration of 40-nm channel length top-gate WS₂ pFET using channel area-selective CVD growth directly on SiO_x/Si substrate. 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. 頁 T244-T245 (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{35cf33757ddb4706bb2f1dc9fab9f1b2,

title = "First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate",

abstract = "Area-selective channel material growth for 2D transistors is more desirable for volume manufacturing than exfoliation or wet/dry transfer after large area growth. We demonstrate the first top-gate WS2 p-channel field-effect transistors (p-FETs) fabricated on SiOx/Si substrate using channel area-selective CVD growth. Smooth and uniform WS2 comprising approximately 6 layers was formed by area-selective CVD growth in which a patterned tungsten-source/drain served as the seed for WS2 growth. For a 40 nm gate length transistor, the device has impressive electrical characteristics: on/off ratio of 106, a S.S. of 97 mV/dec., and nearly zero DIBL.",

author = "Cheng, {Chao Ching} and Chung, {Yun Yan} and Li, {Uing Yang} and Lin, {Chao Ting} and Li, {Chi Feng} and Chen, {Jyun Hong} and Lai, {Tung Yen} and Li, {Kai Shin} and Shieh, {Jia Min} and Su, {Sheng Kai} and Chiang, {Hung Li} and Chen, {Tzu Chiang} and Li, {Lain Jong} and Wong, {H. S.Philip} and Chao-Hsin Chien",

note = "Publisher Copyright: {\textcopyright} 2019 The Japan Society of Applied Physics.; 39th Symposium on VLSI Technology, VLSI Technology 2019 ; Conference date: 09-06-2019 Through 14-06-2019",

year = "2019",

month = jun,

doi = "10.23919/VLSIT.2019.8776498",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "T244--T245",

booktitle = "2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers",

address = "美國",

}

Cheng, CC, Chung, YY, Li, UY, Lin, CT, Li, CF, Chen, JH, Lai, TY, Li, KS, Shieh, JM, Su, SK, Chiang, HL, Chen, TC, Li, LJ, Wong, HSP & Chien, C-H 2019, First demonstration of 40-nm channel length top-gate WS₂ pFET using channel area-selective CVD growth directly on SiO_x/Si substrate. 於 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers., 8776498, Digest of Technical Papers - Symposium on VLSI Technology, 卷 2019-June, Institute of Electrical and Electronics Engineers Inc., 頁 T244-T245, 39th Symposium on VLSI Technology, VLSI Technology 2019, Kyoto, 日本, 9/06/19. https://doi.org/10.23919/VLSIT.2019.8776498

First demonstration of 40-nm channel length top-gate WS₂ pFET using channel area-selective CVD growth directly on SiO_x/Si substrate. / Cheng, Chao Ching; Chung, Yun Yan; Li, Uing Yang 等.
2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. p. T244-T245 8776498 (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2019-June).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate

AU - Cheng, Chao Ching

AU - Chung, Yun Yan

AU - Li, Uing Yang

AU - Lin, Chao Ting

AU - Li, Chi Feng

AU - Chen, Jyun Hong

AU - Lai, Tung Yen

AU - Li, Kai Shin

AU - Shieh, Jia Min

AU - Su, Sheng Kai

AU - Chiang, Hung Li

AU - Chen, Tzu Chiang

AU - Li, Lain Jong

AU - Wong, H. S.Philip

AU - Chien, Chao-Hsin

PY - 2019/6

Y1 - 2019/6

N2 - Area-selective channel material growth for 2D transistors is more desirable for volume manufacturing than exfoliation or wet/dry transfer after large area growth. We demonstrate the first top-gate WS2 p-channel field-effect transistors (p-FETs) fabricated on SiOx/Si substrate using channel area-selective CVD growth. Smooth and uniform WS2 comprising approximately 6 layers was formed by area-selective CVD growth in which a patterned tungsten-source/drain served as the seed for WS2 growth. For a 40 nm gate length transistor, the device has impressive electrical characteristics: on/off ratio of 106, a S.S. of 97 mV/dec., and nearly zero DIBL.

AB - Area-selective channel material growth for 2D transistors is more desirable for volume manufacturing than exfoliation or wet/dry transfer after large area growth. We demonstrate the first top-gate WS2 p-channel field-effect transistors (p-FETs) fabricated on SiOx/Si substrate using channel area-selective CVD growth. Smooth and uniform WS2 comprising approximately 6 layers was formed by area-selective CVD growth in which a patterned tungsten-source/drain served as the seed for WS2 growth. For a 40 nm gate length transistor, the device has impressive electrical characteristics: on/off ratio of 106, a S.S. of 97 mV/dec., and nearly zero DIBL.

UR - http://www.scopus.com/inward/record.url?scp=85070269950&partnerID=8YFLogxK

U2 - 10.23919/VLSIT.2019.8776498

DO - 10.23919/VLSIT.2019.8776498

M3 - Conference contribution

AN - SCOPUS:85070269950

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - T244-T245

BT - 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 39th Symposium on VLSI Technology, VLSI Technology 2019

Y2 - 9 June 2019 through 14 June 2019

ER -

Cheng CC, Chung YY, Li UY, Lin CT, Li CF, Chen JH 等. First demonstration of 40-nm channel length top-gate WS₂ pFET using channel area-selective CVD growth directly on SiO_x/Si substrate. 於 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2019. p. T244-T245. 8776498. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.23919/VLSIT.2019.8776498