摘要
We propose and demonstrate a method which combines film profile engineering (FPE) and a procedure of forming self-aligned bottom gates (SABGs) to fabricate InGaZnO thin-film transistors (TFTs). In the scheme, an ingenious etching procedure was implemented to form the final bottom gate self-aligned to the upper hardmask structure. The fabricated SABG devices show greatly reduced OFF-state leakage as compared with nonself-aligned ones, attributing to the reduction of gate-to-source/drain overlap areas which lowers both parasitic capacitance and gate leakage current. These merits benefit the operation of circuits consisted of TFTs implemented with FPE.
原文 | American English |
---|---|
文章編號 | 7119561 |
頁(從 - 到) | 787-789 |
頁數 | 3 |
期刊 | IEEE Electron Device Letters |
卷 | 36 |
發行號 | 8 |
DOIs | |
出版狀態 | Published - 1 8月 2015 |