Field Plate and Package Optimization for GaN Devices and Systems

Sheng Hsi Hung, Tz Wun Wang, Chien Wei Cho, Po Jui Chiu, Chi Yu Chen, Ke Horng Chen, Kuo Lin Zheng, Chih Chen Li

研究成果: Conference contribution同行評審

摘要

To improve GaN-based system performance, this work demonstrates the 650V GaN field plate (FP) design and the optimized integrated circuit (IC) package. The source FP length is suggested to be longer but less than three times the split high FP (HFP). The connection of the split FP and the 1ST FP to source FP can reduce Coss. Longer 1ST FP and shorter Gap design enhance the Miller ratio and suppress the ringing effect in case of switching. The asynchronous boost converter can be implemented with minimal parasitics and double-sided cooling in a proposed 3D IC package.

原文English
主出版物標題2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9798350361469
DOIs
出版狀態Published - 2024
事件2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024 - Honolulu, 美國
持續時間: 16 6月 202420 6月 2024

出版系列

名字Digest of Technical Papers - Symposium on VLSI Technology
ISSN(列印)0743-1562

Conference

Conference2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
國家/地區美國
城市Honolulu
期間16/06/2420/06/24

指紋

深入研究「Field Plate and Package Optimization for GaN Devices and Systems」主題。共同形成了獨特的指紋。

引用此