FDPrior: A force-directed based parallel partitioning algorithm for three dimensional integrated circuits on GPGPU

Wan Jing Chen*, Hsien Kai Kuo, Tsou Han Chiu, Bo-Cheng Lai

*此作品的通信作者

    研究成果: Conference contribution同行評審

    1 引文 斯高帕斯(Scopus)

    摘要

    This paper proposes an innovative force-directed parallel algorithm, FDPrior, to solve the multilayer partitioning problem of 3DICs. The growing scale and multi-layered structure of the 3DIC technology make it computational expensive for EDA tools to achieve optimization goals. Exploiting the algorithmic parallelism on multi-core architectures becomes the key to attain scalable runtime. By adopting the N-body simulation scheme and novel techniques to reduce synchronization overhead, FDPrior successfully exposes the massive parallelism on the multi-core GPGPU architecture. The objective is to minimize the total number of Through Silicon Vias (TSVs) while meeting the area constraint for each layer. The experimental results on ISPD98 benchmark show that FDPrior outperforms the conventional FM algorithm by achieving in average 5.0X better TSVs and up to 247.3X runtime speedup. Compared with PP3D, a parallel 3DIC partitioning algorithm, FDPrior achieves 6.7X better TSVS with 3.3 X runtime enhancement.

    原文English
    主出版物標題Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
    頁面70-73
    頁數4
    DOIs
    出版狀態Published - 28 6月 2011
    事件2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan
    持續時間: 25 4月 201128 4月 2011

    出版系列

    名字Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

    Conference

    Conference2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
    國家/地區Taiwan
    城市Hsinchu
    期間25/04/1128/04/11

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