Fast WAT test structure for measuring VT variance based on latch-based comparators

Kao Chi Lee, Kai-Chiang Wu, Chih Ying Tsai, Chia-Tso Chao

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

As the technology of IC manufacturing continually scales down, process variations become more and more crucial than before. To statistically characterize local process variations, the traditional array-based test structure measures threshold voltage (Vt) for a sufficiently large number of devices-undertest (DUTs). However, the array-based test structure requires long time for DUT-by-DUT measurement; furthermore, it suffers from significant IR drop or leakage current due to the large number of DUTs, which results in the loss of measurement accuracy. In this paper, we present a novel sense-Amplifierbased test structure that can monitor process variations based on rapid characterization of Vt variance, with marginal error of accuracy. A test-chip containing 120 NMOS and 120 PMOS DUTs has been implemented in 28nm CMOS process technology. Various experiments reveal promising efficiency and accuracy of the proposed test structure, for characterizing Vt variance.

原文English
主出版物標題Proceedings - 2017 IEEE 35th VLSI Test Symposium, VTS 2017
發行者IEEE Computer Society
ISBN(電子)9781509044825
DOIs
出版狀態Published - 15 五月 2017
事件35th IEEE VLSI Test Symposium, VTS 2017 - Las Vegas, United States
持續時間: 9 四月 201712 四月 2017

出版系列

名字Proceedings of the IEEE VLSI Test Symposium

Conference

Conference35th IEEE VLSI Test Symposium, VTS 2017
國家/地區United States
城市Las Vegas
期間9/04/1712/04/17

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