Fast thermal aware placement with accurate thermal analysis based on green function

Sean Shih Ying Liu; Ren Guo Luo; Suradeth Aroonsantidecha; Ching Yu Chin; Hung-Ming Chen

doi:10.1109/TVLSI.2013.2268582

Fast thermal aware placement with accurate thermal analysis based on green function

Sean Shih Ying Liu, Ren Guo Luo, Suradeth Aroonsantidecha, Ching Yu Chin, Hung-Ming Chen

電子研究所

研究成果: Article › 同行評審

12 引文斯高帕斯（Scopus）

摘要

In this paper, we present a fast and accurate thermal aware analytical placer. A thermal model is constructed based on a Green function with discrete cosine transform (DCT) to generate full chip temperature profile. Our thermal model is tightly integrated with an analytical placer implemented based on the SimPL framework. A temperature spreading force based on the Gaussian model is proposed to reduce the maximum on-chip temperature and optimize tradeoff between total half-perimeter wirelength and on-chip maximum temperature. The temperature profile generated using our thermal model is verified by the ANSYS ICEPAK and obtains an average deviation within 3.0% with 240× speedup.

原文	English
文章編號	6553166
頁（從 - 到）	1404-1415
頁數	12
期刊	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
卷	22
發行號	6
DOIs	https://doi.org/10.1109/TVLSI.2013.2268582
出版狀態	Published - 1 1月 2014

存取文件

10.1109/TVLSI.2013.2268582

其它文件與鏈接

Link to publication in Scopus

引用此

@article{a1cc442d08d94d66b85dd8909ef71b63,

title = "Fast thermal aware placement with accurate thermal analysis based on green function",

abstract = "In this paper, we present a fast and accurate thermal aware analytical placer. A thermal model is constructed based on a Green function with discrete cosine transform (DCT) to generate full chip temperature profile. Our thermal model is tightly integrated with an analytical placer implemented based on the SimPL framework. A temperature spreading force based on the Gaussian model is proposed to reduce the maximum on-chip temperature and optimize tradeoff between total half-perimeter wirelength and on-chip maximum temperature. The temperature profile generated using our thermal model is verified by the ANSYS ICEPAK and obtains an average deviation within 3.0% with 240× speedup.",

keywords = "Design for manufacture, design for quality, design methodology, electronic design automation, logic design, placement, temperature control, thermal analysis.",

author = "Liu, {Sean Shih Ying} and Luo, {Ren Guo} and Suradeth Aroonsantidecha and Chin, {Ching Yu} and Hung-Ming Chen",

year = "2014",

month = jan,

day = "1",

doi = "10.1109/TVLSI.2013.2268582",

language = "English",

volume = "22",

pages = "1404--1415",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "6",

}

TY - JOUR

T1 - Fast thermal aware placement with accurate thermal analysis based on green function

AU - Liu, Sean Shih Ying

AU - Luo, Ren Guo

AU - Aroonsantidecha, Suradeth

AU - Chin, Ching Yu

AU - Chen, Hung-Ming

PY - 2014/1/1

Y1 - 2014/1/1

N2 - In this paper, we present a fast and accurate thermal aware analytical placer. A thermal model is constructed based on a Green function with discrete cosine transform (DCT) to generate full chip temperature profile. Our thermal model is tightly integrated with an analytical placer implemented based on the SimPL framework. A temperature spreading force based on the Gaussian model is proposed to reduce the maximum on-chip temperature and optimize tradeoff between total half-perimeter wirelength and on-chip maximum temperature. The temperature profile generated using our thermal model is verified by the ANSYS ICEPAK and obtains an average deviation within 3.0% with 240× speedup.

AB - In this paper, we present a fast and accurate thermal aware analytical placer. A thermal model is constructed based on a Green function with discrete cosine transform (DCT) to generate full chip temperature profile. Our thermal model is tightly integrated with an analytical placer implemented based on the SimPL framework. A temperature spreading force based on the Gaussian model is proposed to reduce the maximum on-chip temperature and optimize tradeoff between total half-perimeter wirelength and on-chip maximum temperature. The temperature profile generated using our thermal model is verified by the ANSYS ICEPAK and obtains an average deviation within 3.0% with 240× speedup.

KW - Design for manufacture

KW - design for quality

KW - design methodology

KW - electronic design automation

KW - logic design

KW - placement

KW - temperature control

KW - thermal analysis.

UR - http://www.scopus.com/inward/record.url?scp=84901623736&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2013.2268582

DO - 10.1109/TVLSI.2013.2268582

M3 - Article

AN - SCOPUS:84901623736

SN - 1063-8210

VL - 22

SP - 1404

EP - 1415

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 6

M1 - 6553166

ER -

Fast thermal aware placement with accurate thermal analysis based on green function

摘要

存取文件

其它文件與鏈接

指紋

引用此