Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications

Duo Sheng*, Ching Che Chung, Chen-Yi Lee

*此作品的通信作者

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)

摘要

A fast-lock and portable all-digital delay-locked loop (ADDLL) with 90° phase shift and tunable digitally-controlled phase shifter (DCPS) for DDR controller applications are presented. The ADDLL can achieve small phase-shift error in 1.3° at 400MHz and locking time of less than 13 clock cycles, making it very suitable for low-power DDR controller with power-down mode. The proposed DCPS provides the suitable phase shift of control signals for DDR interface where precise control is the key to reliable high-performance operation. Besides, the cell-based implementation makes it easy to target a variety of technologies as a soft silicon intellectual property (IP).

原文English
頁(從 - 到)634-639
頁數6
期刊IEICE Electronics Express
7
發行號9
DOIs
出版狀態Published - 10 五月 2010

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