TY - GEN
T1 - Fast analog layout prototyping for nanometer design migration
AU - Weng, Yi Peng
AU - Chen, Hung-Ming
AU - Chen, Tung Chieh
AU - Pan, Po Cheng
AU - Chen, Chien Hung
AU - Chen, Wei-Zen
PY - 2011
Y1 - 2011
N2 - This paper presents an analog layout migration methodology to quickly provide multiple layouts while keeping similar or better circuit performance. Unlike previous works that often generate a single layout that has exactly the same topology with the original layout, this new migration algorithm is able to provide results with different aspect ratios. First, various placement constraints, including topology, matching, and symmetry, are extracted from the original layout. The extracted constraints are hierarchically stored into a topology slicing tree. Placement is performed from the bottom tree nodes to the root tree node. In each tree node, multiple placements for the subtree are recorded. All possible placements under the constraints are recorded in the root node. This algorithm has been successfully applied to a variable gain amplifier and a folded cascode operational amplifier migrating from UMC 90nm to UMC 65nm. The experimental results validate that our approach can provide reasonable layouts, even a better result almost in no time.
AB - This paper presents an analog layout migration methodology to quickly provide multiple layouts while keeping similar or better circuit performance. Unlike previous works that often generate a single layout that has exactly the same topology with the original layout, this new migration algorithm is able to provide results with different aspect ratios. First, various placement constraints, including topology, matching, and symmetry, are extracted from the original layout. The extracted constraints are hierarchically stored into a topology slicing tree. Placement is performed from the bottom tree nodes to the root tree node. In each tree node, multiple placements for the subtree are recorded. All possible placements under the constraints are recorded in the root node. This algorithm has been successfully applied to a variable gain amplifier and a folded cascode operational amplifier migrating from UMC 90nm to UMC 65nm. The experimental results validate that our approach can provide reasonable layouts, even a better result almost in no time.
UR - http://www.scopus.com/inward/record.url?scp=84862943571&partnerID=8YFLogxK
U2 - 10.1109/ICCAD.2011.6105379
DO - 10.1109/ICCAD.2011.6105379
M3 - Conference contribution
AN - SCOPUS:84862943571
SN - 9781457713989
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
SP - 517
EP - 522
BT - 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011
T2 - 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011
Y2 - 7 November 2011 through 10 November 2011
ER -