Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process

Chia Tsen Dai*, Po Yen Chiu, Ming-Dou Ker, Fu Yi Tsai, Yan Hua Peng, Chia Ku Tsai

*此作品的通信作者

    研究成果: Conference contribution同行評審

    3 引文 斯高帕斯(Scopus)

    摘要

    The ESD robustness of gate-driven ESD clamp circuit in a 16-V CMOS process was investigated by the stresses of transmission line pulse (TLP), human-body-model ESD test, and machine-model (MM) ESD test. After TLP stresses of different voltage steps, the same ESD clamp circuit got different secondary breakdown currents (It2). In order to understand such unusual phenomenon, the failure analysis on the TLP-stressed ESD clamp circuits was performed to find the failure mechanism.

    原文English
    主出版物標題2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012
    DOIs
    出版狀態Published - 19 11月 2012
    事件2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012 - Singapore, Singapore
    持續時間: 2 7月 20126 7月 2012

    出版系列

    名字Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

    Conference

    Conference2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012
    國家/地區Singapore
    城市Singapore
    期間2/07/126/07/12

    指紋

    深入研究「Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process」主題。共同形成了獨特的指紋。

    引用此