@inproceedings{4012143b05a44e46a1db809d18f54fd0,
title = "Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process",
abstract = "The ESD robustness of gate-driven ESD clamp circuit in a 16-V CMOS process was investigated by the stresses of transmission line pulse (TLP), human-body-model ESD test, and machine-model (MM) ESD test. After TLP stresses of different voltage steps, the same ESD clamp circuit got different secondary breakdown currents (It2). In order to understand such unusual phenomenon, the failure analysis on the TLP-stressed ESD clamp circuits was performed to find the failure mechanism.",
author = "Dai, {Chia Tsen} and Chiu, {Po Yen} and Ming-Dou Ker and Tsai, {Fu Yi} and Peng, {Yan Hua} and Tsai, {Chia Ku}",
year = "2012",
month = nov,
day = "19",
doi = "10.1109/IPFA.2012.6306283",
language = "English",
isbn = "9781467309806",
series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",
booktitle = "2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012",
note = "2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012 ; Conference date: 02-07-2012 Through 06-07-2012",
}