@inproceedings{8948dc6aae8a464f93b84772155e042e,
title = "Fabrication of Sub-50nm ZnO thin-film transistors with film profile engineering and laminated hardmask structure",
abstract = "We proposed a modified film profile engineering (FPE) process with laminated hardmask (HM) structure to fabricate ZnO thin-film transistors (TFTs) with channel length (L) down to 10 nm. The fabricated ultra-short devices demonstrate uniform and excellent performance. 38 nm ZnO TFTs with discrete TiN gates were also fabricated for suppressing the off-state leakage current.",
author = "Lyu, \{Rong Jhe\} and Horng-Chih Lin and Huang, \{Tiao Yuan\}",
year = "2015",
month = jun,
day = "3",
doi = "10.1109/VLSI-TSA.2015.7117553",
language = "English",
series = "International Symposium on VLSI Technology, Systems, and Applications, Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015",
address = "美國",
note = "2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015 ; Conference date: 27-04-2015 Through 29-04-2015",
}