Fabrication of sub-100-nm metal-oxide-semiconductor field-effect transistors with asymmetrical source/drain using I-line double patterning technique

Horng-Chih Lin*, Tzu I. Tsai, Tien-Sheng Chao, Min Feng Jian, Tiao Yuan Huang

*此作品的通信作者

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)

摘要

The authors present a simple double patterning technique with I-line stepper to define nanoscale structures and have successfully fabricated n -channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with sub-100-nm gate length. With this approach, polycrystalline silicon (poly-Si) gate with linewidth down to 80 nm could be formed with good control, which far exceeds the resolution limit of conventional I-line lithography. Moreover, ineffectiveness of end point detection in the second poly-Si gate definition is also addressed. For reliable process control in the second etching step, appropriate mask design is found to be essential. Finally, sub-100-nm MOSFETs with or without halo implemented symmetrically or asymmetrically are fabricated and characterized.

原文English
文章編號021007
期刊Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics
29
發行號2
DOIs
出版狀態Published - 1 一月 2011

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