Fabrication and characterization of Pi-gate poly-Si junctionless and inversion mode Fin-FETs for 3-D IC applications

Don Ru Hsieh, Jer Yi Lin, Po Yi Kuo, Tien-Sheng Chao

研究成果: Conference contribution同行評審

摘要

In this paper, the Pi-gate (PG) poly-Si junctionless (JL) and inversion mode (IM) Fin-FETs have been successfully fabricated and demonstrated without using costly lithography technique. The PG JL Fin-FETs show excellent electrical performance in terms of low gate overdrive voltage, extremely near-ideal subthreshold swing (S.S.) ∼ 68 mV/dec., steep average subthreshold swing (A.S.S.) ∼ 73 mV/dec., smaller drain induced barrier lowing (DIBL) ∼ 9 mV/V, and higher Ion/Ioff ratio ∼ 1.1 × 108 (VD = 1 V).

原文English
主出版物標題2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016
發行者Institute of Electrical and Electronics Engineers Inc.
頁面110-111
頁數2
ISBN(電子)9781509007264
DOIs
出版狀態Published - 27 9月 2016
事件21st IEEE Silicon Nanoelectronics Workshop, SNW 2016 - Honolulu, United States
持續時間: 12 6月 201613 6月 2016

出版系列

名字2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016

Conference

Conference21st IEEE Silicon Nanoelectronics Workshop, SNW 2016
國家/地區United States
城市Honolulu
期間12/06/1613/06/16

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