The impact of stress effect to the performance of an IGZO panel is discussed in this paper. Depart from conventional method of observing the threshold voltage (Vth) shift, the time dependency of serial ID-VG test is included in building an accurate Vth shift model. The model can be used to simulate the IGZO TFT current change under fixed bias for aiding the circuit design and optimization.
|頁（從 - 到）
|Digest of Technical Papers - SID International Symposium
|Published - 1 6月 2015
|2015 SID International Symposium - San Jose, United States
持續時間: 2 6月 2015 → 3 6月 2015