Extended 0.13 μm CMOS technology for the ultra high-speed and MS/RF application segments

C. S. Chang*, C. P. Chao, Y. K. Leung, C. H. Lin, H. M. Hsu, Y. P. Wang, S. Y. Chang, T. H. Chiu, J. S. Shyu, C. C. Wu, C. H. Wang, R. Y. Chang, C. W. Chen, C. F. Huang, C. H. Chen, S. H. Chen, T. H. Yeh, J. Y. Cheng, J. J. Liaw, Y. L. ChuT. C. Ong, M. C. Yu, C. H. Yu, H. J. Lin, H. J. Tao, M. S. Liang, Y. C. See, C. H. Diaz, Y. C. Sun

*此作品的通信作者

研究成果: Paper同行評審

11 引文 斯高帕斯(Scopus)

摘要

This paper introduces new technology features to support ultra high-speed and MS/RF applications incorporated into a leading-edge fully manufacturable 0.13 μm CMOS foundry technology. New core devices with 15.5 Å and nominal 75 nm physical gate lengths support at least 10% performance improvement with respect to prior release. These devices offer the best Ioff-Idsat performance reported so far for 1.2 V applications. To support high-speed I/O standards, additional 1.8 V-32 Å I/O devices are integrated with the 15.5 Å transistors. Leading-edge passive elements for MS/RF applications are reported in this work. Advanced Cu/low-k back end process integration that can support up to nine layers of metal is also demonstrated.

原文English
頁面68-69
頁數2
出版狀態Published - 2002
事件2002 Symposium on VLSI Technology Digest of Technical Papers - Honolulu, HI, United States
持續時間: 11 六月 200213 六月 2002

Conference

Conference2002 Symposium on VLSI Technology Digest of Technical Papers
國家/地區United States
城市Honolulu, HI
期間11/06/0213/06/02

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