Although modern analog placement algorithms aimed to minimize area and wirelength while satisfying symmetry, proximity, and other placement constraints, the generated layout does not reflect the circuit performance very well because of the routing-induced parasitics on the critical current/signal paths. To simultaneously consider symmetry, wirelength, area utilization, and current/signal paths during analog placement, this paper explores the feasibilities of symmetry islands and monotonic current paths in slicing trees for analog placement optimization. Experimental results show that the proposed formulation and algorithms can generate much more compact layouts resulting in similar or even better circuit performance compared with the previous work.
|頁（從 - 到）||879-892|
|期刊||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|出版狀態||Published - 1 一月 2014|