Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs

Ning Chi Huang, Yu Guang Chen, Kai Chiang Wu

研究成果: Conference contribution同行評審

摘要

Circuit performance has been the key design constraint for over a decade. Variable-latency design (VLD) paradigm was proposed for optimizing the overall performance in terms of throughput. In addition, process variations and aging effects manifest themselves as gate delay shifts, and in turn cause variability of circuit timing (timing variability). Besides, Power consumption is another important design consideration. To deal with the impact of timing variability and power issue better, in this paper, we present a VDD assignment framework based on genetic algorithm (GA) to minimize the power consumption of VLD. Our objective is making constructed VLD circuits more power-efficient under given tolerance to timing variability. Experimental results show that on average our methodology can achieve 24% dynamic power reduction, while preserving at least 8% timing margin, with only 5% overhead in circuit area and leakage power.

原文English
主出版物標題Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
發行者IEEE Computer Society
頁面218-223
頁數6
ISBN(電子)9781538670996
DOIs
出版狀態Published - 7月 2019
事件18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019 - Miami, United States
持續時間: 15 7月 201917 7月 2019

出版系列

名字Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
2019-July
ISSN(列印)2159-3469
ISSN(電子)2159-3477

Conference

Conference18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
國家/地區United States
城市Miami
期間15/07/1917/07/19

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