TY - JOUR
T1 - Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35-μm silicided process
AU - Chen, Tung Yang
AU - Ker, Ming-Dou
AU - Wu, Chung-Yu
PY - 1999
Y1 - 1999
N2 - In this paper, the layout dependence on ESD robustness of NMOS and PMOS devices in a 0.35-μm silicided CMOS process has been experimentally investigated in details. Six 40-pins testchips including 78 different devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.35-μm silicided CMOS process to find the optimal layout rules for the ESD protection devices. The gate-driven effect and substrate-triggered effect on the ESD performance of CMOS devices are also measured and compared. The experimental results show that the substrate-triggered effect is much better than the gate-driven effect to improve ESD robustness of the CMOS devices.
AB - In this paper, the layout dependence on ESD robustness of NMOS and PMOS devices in a 0.35-μm silicided CMOS process has been experimentally investigated in details. Six 40-pins testchips including 78 different devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.35-μm silicided CMOS process to find the optimal layout rules for the ESD protection devices. The gate-driven effect and substrate-triggered effect on the ESD performance of CMOS devices are also measured and compared. The experimental results show that the substrate-triggered effect is much better than the gate-driven effect to improve ESD robustness of the CMOS devices.
UR - http://www.scopus.com/inward/record.url?scp=0032599280&partnerID=8YFLogxK
U2 - 10.1109/VTSA.1999.785993
DO - 10.1109/VTSA.1999.785993
M3 - Conference article
AN - SCOPUS:0032599280
SN - 1524-766X
SP - 35
EP - 38
JO - International Symposium on VLSI Technology, Systems, and Applications, Proceedings
JF - International Symposium on VLSI Technology, Systems, and Applications, Proceedings
T2 - Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications
Y2 - 7 June 1999 through 10 June 1999
ER -