Experimental Demonstration of Stacked Gate-All-Around Poly-Si Nanowires Negative Capacitance FETs with Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process

Shen Yang Lee, Han Wei Chen, Chiuan Huei Shen, Po Yi Kuo, Chun Chih Chung, Yu En Huang, Hsin Yu Chen, Tien Sheng Chao*

*此作品的通信作者

研究成果: Article同行評審

17 引文 斯高帕斯(Scopus)

摘要

For the first time, two-layer stacked nanowire gate-all-around (GAA) negative capacitance (NC) field-effect transistors (FETs) with an ultrasmall poly-Si channel that has a size of 5.3×9 nm2 and a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) are experimentally demonstrated. FETs exhibit a remarkable Ion-Ioff ratio of more than 108. We demonstrated stacked channels, double layers, GAA NC-FET with a threshold voltage (VTH) of 0.61 V, and a superior subthreshold behavior with an average and minimum sub-VTH slope of 43.85 and 26.84 mV/dec, respectively. An additional ZrO2 seed layer was inserted under the Hf1-x ZrxO2 layer to improve ferroelectric crystallinity. Thus, the conventional crystallization annealing step can be omitted due to the presence of the orthorhombic phase (o-phase) before further post-metal annealing (PMA).

原文English
文章編號8835096
頁(從 - 到)1708-1711
頁數4
期刊IEEE Electron Device Letters
40
發行號11
DOIs
出版狀態Published - 11月 2019

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