Experimental Demonstration of Stacked Gate-All-Around Poly-Si Nanowires Negative Capacitance FETs with Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process

For the first time, two-layer stacked nanowire gate-all-around (GAA) negative capacitance (NC) field-effect transistors (FETs) with an ultrasmall poly-Si channel that has a size of 5.3×9 nm² and a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) are experimentally demonstrated. FETs exhibit a remarkable I_on-I_off ratio of more than 10⁸. We demonstrated stacked channels, double layers, GAA NC-FET with a threshold voltage (V_TH) of 0.61 V, and a superior subthreshold behavior with an average and minimum sub-V_TH slope of 43.85 and 26.84 mV/dec, respectively. An additional ZrO₂ seed layer was inserted under the Hf_1-x Zr_xO₂ layer to improve ferroelectric crystallinity. Thus, the conventional crystallization annealing step can be omitted due to the presence of the orthorhombic phase (o-phase) before further post-metal annealing (PMA).