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Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65nm CMOS Technologies
Sam M.H. Hsiao
, Lowry P.T. Wang
, Aaron C.W. Liang
,
Charles H.P. Wen
電機工程學系
開源智能聯網研究中心
研究成果
:
Conference contribution
›
同行評審
4
引文 斯高帕斯(Scopus)
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深入研究「Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65nm CMOS Technologies」主題。共同形成了獨特的指紋。
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Keyphrases
65nm CMOS
100%
Radiation Hardened Latch
100%
Single Event Double Node Upset
100%
Manufacturing Technology
28%
Bulk CMOS
28%
Physical Layout
28%
65 Nm Technology
28%
Latch Design
28%
Environmental Factors
14%
Fin Field-effect Transistor (FinFET)
14%
Process Technology
14%
Technology Node
14%
Circuit Level
14%
Experiment Results
14%
Circuit Reliability
14%
Current Source
14%
Transistor
14%
SPICE Model
14%
Error Probability
14%
Multilevel Framework
14%
TCAD Simulation
14%
Technology Scaling
14%
Scaling Impact
14%
Temperature Variation
14%
Design Style
14%
Device Level
14%
Advanced Technologies
14%
Safety-critical
14%
Storage Elements
14%
Source Modeling
14%
Upsetting
14%
Radiation Hardening by Design
14%
Particle Strike
14%
Voltage Calculation
14%
Strike Angle
14%
Material Science
Electronic Circuit
100%
Tunneling Magnetoresistance
100%
Transistor
50%
Engineering
Nodes
100%
Manufacturing Engineering
22%
Current Source
11%
SPICE
11%
Design Style
11%
Storage Element
11%