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Evaluation of sub-0.2 V high-speed low-power circuits using hetero-channel MOSFET and tunneling FET devices
Yin Nien Chen
*
, Ming Long Fan, Vita Pi Ho Hu,
Pin Su
, Ching Te Chuang
*
此作品的通信作者
電子研究所
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14
引文 斯高帕斯(Scopus)
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Keyphrases
High-speed Low-power
100%
MOSFET
100%
Heteromeric Channel
100%
Low Power Circuits
100%
FET Devices
100%
Tunnel FET
100%
Logic Circuit
28%
Dynamic Power
28%
Device Design
28%
Assist Circuits
28%
Sleep Mode
14%
Process Variation
14%
Inverter
14%
Leakage Current
14%
Device Characteristics
14%
Low Power Operation
14%
Ultra-low
14%
Leakage Power
14%
Temperature Variation
14%
MOSFET Device
14%
Double Oxide
14%
Stand-alone Mode
14%
Temperature Impact
14%
Miller Capacitor
14%
Delay Dynamics
14%
Standby Power
14%
Circuit Area
14%
Engineering
Field Effect Transistor
100%
Tunnel Construction
100%
Metal-Oxide-Semiconductor Field-Effect Transistor
100%
Energy Engineering
25%
Logic Circuit
25%
Low Power Operation
12%
Sleep Mode
12%
Miller Capacitance
12%
Inverter
12%
Process Variation
12%