Evaluation of RF and logic performance for 80 nm InAs/InGaAs composite channel HEMTs using gate sinking technology

Chien I. Kuo; Heng-Tung Hsu; Chia Yuan Chang; Edward Yi Chang; Heng Shou Hsu

doi:10.1109/EDSSC.2007.4450110

Evaluation of RF and logic performance for 80 nm InAs/InGaAs composite channel HEMTs using gate sinking technology

Chien I. Kuo^*, Heng-Tung Hsu, Chia Yuan Chang, Edward Yi Chang, Heng Shou Hsu

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

2 引文斯高帕斯（Scopus）

摘要

80-nm-gate In_0.7Ga_0.3As/InAs/In_0.7Ga _0.3As composite channel high-electron mobility transistors (HEMTs) fabricated using platinum (Pt) buried gate as the Schottky contact metal were evaluated for RF and logic application. After gate sinking at the 250°C for 3 minutes, the device exhibited a high g_m value of 1590mS/mm at V_d = 0.5V and the current gain cutoff frequency f_T was measured to be 494 GHz. The intrinsic gate delay time was calculated to be 0.78 psec at supply voltage of 0.6 V. This is the highest f_T achieved for 80 nm gate length HEMT devices. These superior performances are attributed to the reduction of distance between gate and channel, and the reduction of parasitic gate capacitances during gate-sinking process.

原文	English
主出版物標題	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
頁面	255-258
頁數	4
DOIs	https://doi.org/10.1109/EDSSC.2007.4450110
出版狀態	Published - 2007
事件	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan, 台灣持續時間: 20 12月 2007 → 22 12月 2007

出版系列

名字	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

Conference

Conference	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
國家/地區	台灣
城市	Tainan
期間	20/12/07 → 22/12/07

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10.1109/EDSSC.2007.4450110

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Link to publication in Scopus

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Kuo, C. I., Hsu, H.-T., Chang, C. Y., Chang, E. Y., & Hsu, H. S. (2007). Evaluation of RF and logic performance for 80 nm InAs/InGaAs composite channel HEMTs using gate sinking technology. 於 IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 (頁 255-258). 文章 4450110 (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007). https://doi.org/10.1109/EDSSC.2007.4450110

@inproceedings{52830077df7a4aa886d400bd966f48ef,

title = "Evaluation of RF and logic performance for 80 nm InAs/InGaAs composite channel HEMTs using gate sinking technology",

abstract = "80-nm-gate In0.7Ga0.3As/InAs/In0.7Ga 0.3As composite channel high-electron mobility transistors (HEMTs) fabricated using platinum (Pt) buried gate as the Schottky contact metal were evaluated for RF and logic application. After gate sinking at the 250°C for 3 minutes, the device exhibited a high gm value of 1590mS/mm at Vd = 0.5V and the current gain cutoff frequency fT was measured to be 494 GHz. The intrinsic gate delay time was calculated to be 0.78 psec at supply voltage of 0.6 V. This is the highest fT achieved for 80 nm gate length HEMT devices. These superior performances are attributed to the reduction of distance between gate and channel, and the reduction of parasitic gate capacitances during gate-sinking process.",

author = "Kuo, {Chien I.} and Heng-Tung Hsu and Chang, {Chia Yuan} and Chang, {Edward Yi} and Hsu, {Heng Shou}",

year = "2007",

doi = "10.1109/EDSSC.2007.4450110",

language = "English",

isbn = "1424406374",

series = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007",

pages = "255--258",

booktitle = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007",

note = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 ; Conference date: 20-12-2007 Through 22-12-2007",

}

Kuo, CI, Hsu, H-T, Chang, CY, Chang, EY & Hsu, HS 2007, Evaluation of RF and logic performance for 80 nm InAs/InGaAs composite channel HEMTs using gate sinking technology. 於 IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007., 4450110, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007, 頁 255-258, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007, Tainan, 台灣, 20/12/07. https://doi.org/10.1109/EDSSC.2007.4450110

Evaluation of RF and logic performance for 80 nm InAs/InGaAs composite channel HEMTs using gate sinking technology. / Kuo, Chien I.; Hsu, Heng-Tung; Chang, Chia Yuan 等.
IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. 2007. p. 255-258 4450110 (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Evaluation of RF and logic performance for 80 nm InAs/InGaAs composite channel HEMTs using gate sinking technology

AU - Kuo, Chien I.

AU - Hsu, Heng-Tung

AU - Chang, Chia Yuan

AU - Chang, Edward Yi

AU - Hsu, Heng Shou

PY - 2007

Y1 - 2007

N2 - 80-nm-gate In0.7Ga0.3As/InAs/In0.7Ga 0.3As composite channel high-electron mobility transistors (HEMTs) fabricated using platinum (Pt) buried gate as the Schottky contact metal were evaluated for RF and logic application. After gate sinking at the 250°C for 3 minutes, the device exhibited a high gm value of 1590mS/mm at Vd = 0.5V and the current gain cutoff frequency fT was measured to be 494 GHz. The intrinsic gate delay time was calculated to be 0.78 psec at supply voltage of 0.6 V. This is the highest fT achieved for 80 nm gate length HEMT devices. These superior performances are attributed to the reduction of distance between gate and channel, and the reduction of parasitic gate capacitances during gate-sinking process.

AB - 80-nm-gate In0.7Ga0.3As/InAs/In0.7Ga 0.3As composite channel high-electron mobility transistors (HEMTs) fabricated using platinum (Pt) buried gate as the Schottky contact metal were evaluated for RF and logic application. After gate sinking at the 250°C for 3 minutes, the device exhibited a high gm value of 1590mS/mm at Vd = 0.5V and the current gain cutoff frequency fT was measured to be 494 GHz. The intrinsic gate delay time was calculated to be 0.78 psec at supply voltage of 0.6 V. This is the highest fT achieved for 80 nm gate length HEMT devices. These superior performances are attributed to the reduction of distance between gate and channel, and the reduction of parasitic gate capacitances during gate-sinking process.

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U2 - 10.1109/EDSSC.2007.4450110

DO - 10.1109/EDSSC.2007.4450110

M3 - Conference contribution

AN - SCOPUS:43049181539

SN - 1424406374

SN - 9781424406371

T3 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

SP - 255

EP - 258

BT - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

T2 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

Y2 - 20 December 2007 through 22 December 2007

ER -

Kuo CI, Hsu HT, Chang CY, Chang EY, Hsu HS. Evaluation of RF and logic performance for 80 nm InAs/InGaAs composite channel HEMTs using gate sinking technology. 於 IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. 2007. p. 255-258. 4450110. (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007). doi: 10.1109/EDSSC.2007.4450110

Evaluation of RF and logic performance for 80 nm InAs/InGaAs composite channel HEMTs using gate sinking technology

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